URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmac.cgs] - Rev 227
Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for WMAC# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global wmacwmac:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Unsigned, Multiply Accumulate, Non-zeroingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x22222222mvi_h_gr r4, 0x33333333mvi_h_gr r5, 0x44444444tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wmacu wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x22222222test_h_gr r4, 0x6c889377test_h_gr r5, 0x44444444# Test Unsigned, Multiply Accumulate, Zeroingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x22222222mvi_h_gr r4, 0x33333333mvi_h_gr r5, 0x44444444tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wmacuz wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x22222222test_h_gr r4, 0x39556044test_h_gr r5, 0x00000000# Test Signed, Multiply Accumulate, Non-zeroingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x22222222mvi_h_gr r4, 0x33333333mvi_h_gr r5, 0x44444444tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wmacs wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x22222222test_h_gr r4, 0x28449377test_h_gr r5, 0x44444444# Test Signed, Multiply Accumulate, Zeroingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x22222222mvi_h_gr r4, 0x33333333mvi_h_gr r5, 0x44444444tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wmacsz wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x22222222test_h_gr r4, 0xf5116044test_h_gr r5, 0xffffffffpass