URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [csra.cgs] - Rev 227
Compare with Previous | Blame | View Log
# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond# mach: all.include "testutils.inc"start.global csracsra:set_spr_immed 0x1b1b,cccrset_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc0,1test_icc 0 1 0 1 icc0test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc0,1test_icc 1 1 1 1 icc0test_gr_limmed 0xc000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc4,1test_icc 1 1 1 1 icc0test_gr_immed -1,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc4,1test_icc 1 0 1 0 icc0test_gr_immed 0x00000000,gr8set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc0,0test_icc 0 1 0 1 icc0test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc0,0test_icc 1 1 1 1 icc0test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc4,0test_icc 1 1 1 1 icc0test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,0 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc4,0test_icc 1 0 1 0 icc0test_gr_limmed 0x4000,0x0000,gr8set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc1,0test_icc 0 1 0 1 icc1test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc1,0test_icc 1 1 1 1 icc1test_gr_limmed 0xc000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc5,0test_icc 1 1 1 1 icc1test_gr_immed -1,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc5,0test_icc 1 0 1 0 icc1test_gr_immed 0x00000000,gr8set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc1,1test_icc 0 1 0 1 icc1test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc1,1test_icc 1 1 1 1 icc1test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc5,1test_icc 1 1 1 1 icc1test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,1 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc5,1test_icc 1 0 1 0 icc1test_gr_limmed 0x4000,0x0000,gr8set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,2 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc2,0test_icc 0 1 0 1 icc2test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,2 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc2,0test_icc 1 1 1 1 icc2test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,2 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc6,1test_icc 1 1 1 1 icc2test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,2 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc6,1test_icc 1 0 1 0 icc2test_gr_limmed 0x4000,0x0000,gr8set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0set_gr_limmed 0x8000,0x0000,gr8set_icc 0x05,3 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc3,0test_icc 0 1 0 1 icc3test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,3 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc3,0test_icc 1 1 1 1 icc3test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31set_gr_limmed 0x8000,0x0000,gr8set_icc 0x0f,3 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc7,1test_icc 1 1 1 1 icc3test_gr_limmed 0x8000,0x0000,gr8set_gr_limmed 0xdead,0xbeff,gr7 ; clear registerset_gr_limmed 0x4000,0x0000,gr8set_icc 0x0a,3 ; Set mask opposite of expectedcsra gr8,gr7,gr8,cc7,1test_icc 1 0 1 0 icc3test_gr_limmed 0x4000,0x0000,gr8pass