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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [fr500/] [cmqaddhus.cgs] - Rev 227
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# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond# mach: frv fr500.include "../testutils.inc"start.global cmqaddhuscmqaddhus:set_spr_immed 0x1b1b,cccrset_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc0,1test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0xdead,0xbeef,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc0,1test_fr_limmed 0xbeef,0xdead,fr14test_fr_limmed 0x2345,0x6789,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc4,1test_fr_limmed 0x8000,0x7fff,fr14test_fr_limmed 0xffff,0xffff,fr15test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc4,1cmqaddhus fr12,fr12,fr16,cc4,1test_fr_limmed 0x0004,0x0002,fr14test_fr_limmed 0x0002,0x0002,fr15test_fr_limmed 0xffff,0xffff,fr16test_fr_limmed 0xffff,0xffff,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc1,0test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0xdead,0xbeef,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc1,0test_fr_limmed 0xbeef,0xdead,fr14test_fr_limmed 0x2345,0x6789,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc5,0test_fr_limmed 0x8000,0x7fff,fr14test_fr_limmed 0xffff,0xffff,fr15test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc5,0cmqaddhus fr12,fr12,fr16,cc5,0test_fr_limmed 0x0004,0x0002,fr14test_fr_limmed 0x0002,0x0002,fr15test_fr_limmed 0xffff,0xffff,fr16test_fr_limmed 0xffff,0xffff,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc0,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc0,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc4,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc4,0cmqaddhus fr12,fr12,fr16,cc4,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc1,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc1,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc5,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc5,1cmqaddhus fr12,fr12,fr16,cc5,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc2,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc2,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc6,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc6,0cmqaddhus fr12,fr12,fr16,cc6,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqaddhus fr10,fr12,fr14,cc3,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqaddhus fr10,fr12,fr14,cc3,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xfffe,fr11set_fr_iimmed 0x0002,0x0001,fr12set_fr_iimmed 0x0001,0x0002,fr13cmqaddhus fr10,fr12,fr14,cc7,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0002,0x0001,fr10set_fr_iimmed 0x0001,0x0001,fr11set_fr_iimmed 0xfffe,0xfffe,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqaddhus.p fr10,fr10,fr14,cc7,0cmqaddhus fr12,fr12,fr16,cc7,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setpass