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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [mqxmachs.cgs] - Rev 227
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# frv testcase for mqxmachs $GRi,$GRj,$ACCk# mach: fr400.include "testutils.inc"start.global mqxmachsmqxmachs:; Positive operandsset_fr_iimmed 2,3,fr8 ; multiply small numbersset_fr_iimmed 3,2,fr10set_fr_iimmed 0,1,fr9 ; multiply by 0set_fr_iimmed 2,0,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1test_accg_immed 0,accg2test_acc_immed 6,acc2test_accg_immed 0,accg3test_acc_immed 6,acc3set_fr_iimmed 2,1,fr8 ; multiply by 1set_fr_iimmed 1,2,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_immed 8,acc2test_accg_immed 0,accg3test_acc_immed 8,acc3test_accg_immed 0,accg0test_acc_limmed 0,0x7ffe,acc0test_accg_immed 0,accg1test_acc_limmed 0,0x7ffe,acc1set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_limmed 0x0000,0x8008,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x8008,acc3test_accg_immed 0,accg0test_acc_limmed 0x3fff,0x7fff,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0x7fff,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr8 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr10set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1set_fr_iimmed 1,0xfffe,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_limmed 0x0000,0x8002,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x8002,acc3test_accg_immed 0,accg0test_acc_limmed 0x3fff,0x7ffd,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0x7ffd,acc1set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0set_fr_iimmed 0,0xfffe,fr10set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_limmed 0x0000,0x8002,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x8002,acc3test_accg_immed 0,accg0test_acc_limmed 0x3fff,0x3ffb,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0x3ffb,acc1set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr10set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_limmed 0x0000,0x0002,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x0002,acc3test_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xbffb,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xbffb,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr10set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_limmed 0x0000,0x0008,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x0008,acc3test_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xbffd,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xbffd,acc1set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg2test_acc_immed 0x3fff0009,acc2test_accg_immed 0,accg3test_acc_immed 0x3fff0009,acc3test_accg_immed 0,accg0test_acc_immed 0x3fffbffd,acc0test_accg_immed 0,accg1test_acc_immed 0x3fffbffd,acc1set_accg_immed 0x7f,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0x7f,accg3set_acc_immed 0xffffffff,acc3set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x7f,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0x7f,accg3test_acc_limmed 0xffff,0xffff,acc3test_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1set_accg_immed 0x80,accg2 ; saturationset_acc_immed 0,acc2set_accg_immed 0x80,accg3set_acc_immed 0,acc3set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr8set_fr_iimmed 1,0xffff,fr10set_fr_iimmed 0x0000,0x8000,fr9 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr11mqxmachs fr8,fr10,acc0test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg2test_acc_immed 0,acc2test_accg_immed 0x80,accg3test_acc_immed 0,acc3test_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1pass