OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [addv3.cgs] - Rev 227

Compare with Previous | Blame | View Log

# m32r testcase for addv3 $dr,$sr,#$simm16
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global addv3
addv3:
        mvi_h_condbit 0
        mvi_h_gr r4, 1
        mvi_h_gr r5, 1

        addv3 r4, r5, #2

        bc not_ok

        test_h_gr r4, 3

        mvi_h_gr r5, 0x7fff8001

        addv3 r4, r5, #0x7fff

        bnc not_ok

        pass
not_ok:
        fail

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.