OpenCores

URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [and3.cgs] - Rev 227

Compare with Previous | Blame | View Log

# m32r testcase for and3 $dr,$sr,#$uimm16
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global and3
and3:
        mvi_h_gr r4, 0
        mvi_h_gr r5, 6

        and3 r4, r5, #3

        test_h_gr r4, 2

        pass

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.