OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [iq2000/] [Makefile.in] - Rev 381

Go to most recent revision | Compare with Previous | Blame | View Log

# Makefile template for Configure for the IQ2000 simulator
# Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.

## COMMON_PRE_CONFIG_FRAG

IQ2000_OBJS = iq2000.o cpu.o decode.o sem.o model.o mloop.o

CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =

SIM_OBJS = \
        $(SIM_NEW_COMMON_OBJS) \
        sim-cpu.o \
        sim-hload.o \
        sim-hrw.o \
        sim-model.o \
        sim-reg.o \
        cgen-utils.o cgen-trace.o cgen-scache.o \
        cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
        sim-if.o arch.o \
        $(IQ2000_OBJS) \
        $(CONFIG_DEVICES)

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
        $(CGEN_INCLUDE_DEPS) \
        arch.h cpuall.h iq2000-sim.h $(srcdir)/../../opcodes/iq2000-desc.h

SIM_EXTRA_CFLAGS =

ALL_CPU_CFLAGS = -DHAVE_CPU_IQ2000BF -DHAVE_CPU_IQ10BF

SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = iq2000-clean

## COMMON_POST_CONFIG_FRAG

arch = iq2000

sim-if.o: $(srcdir)/sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h

arch.o: arch.c $(SIM_MAIN_DEPS)
        $(CC) -c $(srcdir)/arch.c $(ALL_CFLAGS) -UHAVE_CPU_IQ10BF

devices.o: $(srcdir)/devices.c $(SIM_MAIN_DEPS)

# IQ2000 objs

IQ2000BF_INCLUDE_DEPS = \
        $(CGEN_MAIN_CPU_DEPS) \
        cpu.h decode.h eng.h

iq2000.o: $(srcdir)/iq2000.c $(IQ2000BF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop.c eng.h: stamp-mloop
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
        $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
                -mono -fast -pbb -switch sem-switch.c \
                -cpu iq2000bf -infile $(srcdir)/mloop.in
        $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
        $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
        touch stamp-mloop
mloop.o: mloop.c $(srcdir)/sem-switch.c $(IQ2000BF_INCLUDE_DEPS)

cpu.o: $(srcdir)/cpu.c $(IQ2000BF_INCLUDE_DEPS)
decode.o: $(srcdir)/decode.c $(IQ2000BF_INCLUDE_DEPS)
sem.o: $(srcdir)/sem.c $(IQ2000BF_INCLUDE_DEPS)
model.o: $(srcdir)/model.c $(IQ2000BF_INCLUDE_DEPS)

iq2000-clean:
        rm -f mloop.c eng.h stamp-mloop
        rm -f tmp-*
        rm -f stamp-arch stamp-cpu

# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/iq2000.cpu Makefile
        $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=iq2000 \
          archfile=$(CPU_DIR)/iq2000.cpu \
          FLAGS="with-scache with-profile=fn"
        touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
        @true

stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/iq2000.cpu Makefile
        $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
          cpu=iq2000bf mach=iq2000 \
          archfile=$(CPU_DIR)/iq2000.cpu \
          FLAGS="with-scache with-profile=fn" \
          EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
        touch stamp-cpu
cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
        @true

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.