OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [common/] [Makefile.in] - Rev 367

Go to most recent revision | Compare with Previous | Blame | View Log

CC=gcc
CFLAGS = -Wall -Werror -I../../common -I../../../include -g
default: check


# Verify SIM-BITS

check: bits32m0.ok bits32m31.ok bits64m0.ok bits64m63.ok
all: bits32m0 bits32m31 bits64m0 bits64m63

bits32m0.c: bits-gen bits-tst.c
        ./bits-gen 32 0 big > tmp-bits32m0.c
        cat bits-tst.c >> tmp-bits32m0.c
        mv tmp-bits32m0.c bits32m0.c
bits32m31.c: bits-gen bits-tst.c
        ./bits-gen 32 31 little > tmp-bits32m31.c
        cat bits-tst.c >> tmp-bits32m31.c
        mv tmp-bits32m31.c bits32m31.c
bits64m0.c: bits-gen bits-tst.c
        ./bits-gen 64 0 big > tmp-bits64m0.c
        cat bits-tst.c >> tmp-bits64m0.c
        mv tmp-bits64m0.c bits64m0.c
bits64m63.c: bits-gen bits-tst.c
        ./bits-gen 64 63 little > tmp-bits64m63.c
        cat bits-tst.c >> tmp-bits64m63.c
        mv tmp-bits64m63.c bits64m63.c



# Verify SIM-FPU
#
#check: fpu-tst.ok
#all: fpu-tst



# Verify SIM-ALU

check: alu-tst.ok
all: alu-tst
alu-tst.o: alu-tst.c alu-n-tst.h

clean:
        rm -f *.o
        rm -f *.ok
        rm -f bits32m0 bits32m31 bits64m0 bits64m63 bits-gen
        rm -f tmp-*
        rm -f alu-tst

.SUFIXES: .ok
%.ok: %
        ./$<
        touch $<.ok

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.