OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fblg.cgs] - Rev 373

Go to most recent revision | Compare with Previous | Blame | View Log

# frv testcase for fblg $FCCi,$hint,$label16
# mach: all

        .include "testutils.inc"

        start

        .global fblg
fblg:
        set_fcc         0x0 0
        fblg            fcc0,0,bad
        set_fcc         0x1 1
        fblg            fcc1,1,bad
        set_fcc         0x2 2
        fblg            fcc2,2,ok3
        fail
ok3:
        set_fcc         0x3 3
        fblg            fcc3,3,ok4
        fail
ok4:
        set_fcc         0x4 0
        fblg            fcc0,0,ok5
        fail
ok5:
        set_fcc         0x5 1
        fblg            fcc1,1,ok6
        fail
ok6:
        set_fcc         0x6 2
        fblg            fcc2,2,ok7
        fail
ok7:
        set_fcc         0x7 3
        fblg            fcc3,3,ok8
        fail
ok8:
        set_fcc         0x8 0
        fblg            fcc0,0,bad
        set_fcc         0x9 1
        fblg            fcc1,1,bad
        set_fcc         0xa 2
        fblg            fcc2,2,okb
        fail
okb:
        set_fcc         0xb 3
        fblg            fcc3,3,okc
        fail
okc:
        set_fcc         0xc 0
        fblg            fcc0,0,okd
        fail
okd:
        set_fcc         0xd 1
        fblg            fcc1,1,oke
        fail
oke:
        set_fcc         0xe 2
        fblg            fcc2,2,okf
        fail
okf:
        set_fcc         0xf 3
        fblg            fcc3,3,okg
        fail
okg:

        pass
bad:
        fail

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.