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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr500/] [dcul.cgs] - Rev 373
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# FRV testcase for dcul GRi# mach: frv fr500.include "../testutils.inc"start.global dculdcul:or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode; preload and lock all the lines in set 0 of the data cacheset_gr_immed 0x70000,gr10lock_data_cache gr10set_mem_immed 0x11111111,gr10test_mem_immed 0x11111111,gr10inc_gr_immed 0x1000,gr10set_gr_immed 1,gr11lock_data_cache gr10set_mem_immed 0x22222222,gr10test_mem_immed 0x22222222,gr10inc_gr_immed 0x1000,gr10set_gr_immed 63,gr11lock_data_cache gr10set_mem_immed 0x33333333,gr10test_mem_immed 0x33333333,gr10inc_gr_immed 0x1000,gr10set_gr_immed 64,gr11lock_data_cache gr10set_mem_immed 0x44444444,gr10test_mem_immed 0x44444444,gr10; Now write to another address which should be in the same set; the write should go through to memory, since all the lines in the; set are lockedinc_gr_immed 0x1000,gr10set_mem_immed 0xdeadbeef,gr10test_mem_immed 0xdeadbeef,gr10; Invalidate the data cache. Only the last value stored should have made; it through to memoryset_gr_immed 0x70000,gr10invalidate_data_cache gr10test_mem_immed 0,gr10inc_gr_immed 0x1000,gr10invalidate_data_cache gr10test_mem_immed 0,gr10inc_gr_immed 0x1000,gr10invalidate_data_cache gr10test_mem_immed 0,gr10inc_gr_immed 0x1000,gr10invalidate_data_cache gr10test_mem_immed 0,gr10inc_gr_immed 0x1000,gr10invalidate_data_cache gr10test_mem_immed 0xdeadbeef,gr10; Now preload load and lock all the lines in set 0 of the data cache; againset_gr_immed 0x70000,gr10lock_data_cache gr10set_mem_immed 0x11111111,gr10test_mem_immed 0x11111111,gr10inc_gr_immed 0x1000,gr10set_gr_immed 1,gr11lock_data_cache gr10set_mem_immed 0x22222222,gr10test_mem_immed 0x22222222,gr10inc_gr_immed 0x1000,gr10set_gr_immed 63,gr11lock_data_cache gr10set_mem_immed 0x33333333,gr10test_mem_immed 0x33333333,gr10inc_gr_immed 0x1000,gr10set_gr_immed 64,gr11lock_data_cache gr10set_mem_immed 0x44444444,gr10test_mem_immed 0x44444444,gr10; unlock one lineset_gr_immed 0x72000,gr10dcul gr10; Now write to another address which should be in the same set.set_gr_immed 0x75000,gr10set_mem_immed 0xbeefdead,gr10; All of the stored values should be retrievableset_gr_immed 0x70000,gr10test_mem_immed 0x11111111,gr10inc_gr_immed 0x1000,gr10test_mem_immed 0x22222222,gr10inc_gr_immed 0x1000,gr10test_mem_immed 0x33333333,gr10inc_gr_immed 0x1000,gr10test_mem_immed 0x44444444,gr10inc_gr_immed 0x1000,gr10test_mem_immed 0xdeadbeef,gr10inc_gr_immed 0x1000,gr10test_mem_immed 0xbeefdead,gr10pass
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