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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [interrupts/] [shadow_regs.cgs] - Rev 330
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# FRV testcase for handling of shadow registers SR0-SR4# mach: frv.include "testutils.inc"start.global tratra:test_spr_bits 0x800,11,1,psr ; PSR.ESR settest_spr_bits 0x4,2,1,psr ; PSR.S set; Set up exception handler for laterand_spr_immed -4081,tbr ; clear tbr.ttset_gr_spr tbr,gr7inc_gr_immed 2112,gr7 ; address of exception handlerset_bctrlr_0_0 gr7 ; bctrlr 0,0set_spr_immed 128,lcrset_psr_et 1set_gr_immed 0x11111111,gr4 ; SGR4-7set_gr_immed 0x22222222,gr5set_gr_immed 0x33333333,gr6set_gr_immed 0x44444444,gr7set_spr_immed 0x55555555,sr0 ; UGR4-7set_spr_immed 0x66666666,sr1set_spr_immed 0x77777777,sr2set_spr_immed 0x88888888,sr3and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESRtest_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3set_spr_immed 0x55555555,sr0 ; SGR4-7set_spr_immed 0x66666666,sr1set_spr_immed 0x77777777,sr2set_spr_immed 0x88888888,sr3test_gr_immed 0x55555555,gr4 ; SGR4-7test_gr_immed 0x66666666,gr5test_gr_immed 0x77777777,gr6test_gr_immed 0x88888888,gr7test_spr_immed 0x55555555,sr0 ; SGR4-7test_spr_immed 0x66666666,sr1test_spr_immed 0x77777777,sr2test_spr_immed 0x88888888,sr3set_gr_immed 0x11111111,gr4 ; SGR4-7set_gr_immed 0x22222222,gr5set_gr_immed 0x33333333,gr6set_gr_immed 0x44444444,gr7test_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3or_spr_immed 0x00000800,psr ; turn on PSR.ESRtest_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefinedtest_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7set_spr_immed 0x55555555,sr0 ; UGR4-7set_spr_immed 0x66666666,sr1set_spr_immed 0x77777777,sr2set_spr_immed 0x88888888,sr3test_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x55555555,sr0 ; UGR4-7test_spr_immed 0x66666666,sr1test_spr_immed 0x77777777,sr2test_spr_immed 0x88888888,sr3and_spr_immed 0xfffffffb,psr ; turn off PSR.Stest_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3test_gr_immed 0x55555555,gr4 ; UGR4-7test_gr_immed 0x66666666,gr5test_gr_immed 0x77777777,gr6test_gr_immed 0x88888888,gr7; need to generate a trap to return to supervisor modeset_spr_addr ok0,lrtira gr0,4 ; should branch to tbr + (128 + 4)*16test_spr_bits 0x800,11,0,psr ; PSR.ESR cleartest_spr_bits 0x4,2,0,psr ; PSR.S cleartest_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3set_gr_immed 0x55555555,gr4 ; SGR4-7set_gr_immed 0x66666666,gr5set_gr_immed 0x77777777,gr6set_gr_immed 0x88888888,gr7test_gr_immed 0x55555555,gr4 ; SGR4-7test_gr_immed 0x66666666,gr5test_gr_immed 0x77777777,gr6test_gr_immed 0x88888888,gr7test_spr_immed 0x55555555,sr0 ; SGR4-7test_spr_immed 0x66666666,sr1test_spr_immed 0x77777777,sr2test_spr_immed 0x88888888,sr3set_gr_immed 0x11111111,gr4 ; SGR4-7set_gr_immed 0x22222222,gr5set_gr_immed 0x33333333,gr6set_gr_immed 0x44444444,gr7test_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3; need to generate a trap to return to supervisor modeset_spr_addr ok1,lrtira gr0,4 ; should branch to tbr + (128 + 4)*16passok0: ; exception handler should branch here the first timetest_spr_bits 0x800,11,1,psr ; PSR.ESR settest_spr_bits 0x4,2,1,psr ; PSR.S settest_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x55555555,sr0 ; UGR4-7test_spr_immed 0x66666666,sr1test_spr_immed 0x77777777,sr2test_spr_immed 0x88888888,sr3and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESRtest_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3rett 0failok1: ; exception handler should branch here the second timetest_spr_bits 0x800,11,0,psr ; PSR.ESR cleartest_spr_bits 0x4,2,1,psr ; PSR.S settest_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3set_spr_immed 0x55555555,sr0 ; SGR4-7set_spr_immed 0x66666666,sr1set_spr_immed 0x77777777,sr2set_spr_immed 0x88888888,sr3test_gr_immed 0x55555555,gr4 ; SGR4-7test_gr_immed 0x66666666,gr5test_gr_immed 0x77777777,gr6test_gr_immed 0x88888888,gr7test_spr_immed 0x55555555,sr0 ; SGR4-7test_spr_immed 0x66666666,sr1test_spr_immed 0x77777777,sr2test_spr_immed 0x88888888,sr3set_gr_immed 0x11111111,gr4 ; SGR4-7set_gr_immed 0x22222222,gr5set_gr_immed 0x33333333,gr6set_gr_immed 0x44444444,gr7test_gr_immed 0x11111111,gr4 ; SGR4-7test_gr_immed 0x22222222,gr5test_gr_immed 0x33333333,gr6test_gr_immed 0x44444444,gr7test_spr_immed 0x11111111,sr0 ; SGR4-7test_spr_immed 0x22222222,sr1test_spr_immed 0x33333333,sr2test_spr_immed 0x44444444,sr3rett 0fail