OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [m32r/] [rach.cgs] - Rev 330

Compare with Previous | Blame | View Log

# m32r testcase for rach
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global rach
rach:
        mvi_h_accum0 1, 0x40004001
        rach
        test_h_accum0 3, 0

        mvi_h_accum0 0x3fff, 0xc0000000
        rach
        test_h_accum0 0x7fff, 0

        mvi_h_accum0 0xffff8000, 0
        rach
        test_h_accum0 0xffff8000, 0

        pass

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.