URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [m32c/] [genscript] - Rev 307
Go to most recent revision | Compare with Previous | Blame | View Log
#!/bin/sh
# Copyright (c) 2005 Red Hat Incorporated.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# The name of Red Hat Incorporated may not be used to endorse
# or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
srcdir="$1"
name="$2"
ramstart="$3"
ramsize="$4"
romstart="$5"
romsize="$6"
vecprefix="$7"
sedcmd="s/RAMSTART/$ramstart/g; s/RAMSIZE/$ramsize/g"
sedcmd="$sedcmd; s/ROMSTART/$romstart/g; s/ROMSIZE/$romsize/g"
# .rodata can be left with .text
rotext='/IF_ROCOPY/d'
# .rodata needs to be with .data
rodata='/IF_ROROM/d'
# All sections are put in one region
simram='s/LOWROM/RAM/g; s/= .*SIZEOF.*/= 0);/; s/AT>ROM//g'
oneram='s/> ROM/> RAM/g;'
# RW data needs to be copied to RAM
rwonly='s/LOWROM/ROM/g; s/ SIZEOF(.rodata) + //g'
# all data needs to be copied to RAM
rocopy='s/LOWROM/RAM AT>ROM/g'
case $name:$romstart in
sim*:0 )
# The r8c and m32c simulators have only a single memory region
sedcmd="$sedcmd; $simram; $oneram; $rotext"
;;
sim*:* )
# This is most likely the m16c simulator
sedcmd="$sedcmd; $simram; $rodata"
;;
*:0x???? )
# This is most likely the r8c chip
sedcmd="$sedcmd; $rwonly; $rotext"
;;
m32*:* )
sedcmd="$sedcmd; $rwonly; $rotext"
;;
*:* )
sedcmd="$sedcmd; $rocopy; $rodata"
;;
esac
sedcmd="$sedcmd; /ORIGIN = 0,/d"
sedcmd="$sedcmd; s/VECSTART/${vecprefix}dc/; s/RESETSTART/${vecprefix}fc/"
sed "$sedcmd" < ${srcdir}/m32c.tmpl > ${name}.ld
Go to most recent revision | Compare with Previous | Blame | View Log