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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [or32/] [sim.cfg] - Rev 301
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/* sim.cfg -- Simulator config file for use with Newlib
*
* Copyright (C) 2010, Embecosm Limited <info@embecosm.com>
*
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of Newlib.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc., 675
* Mass Ave, Cambridge, MA 02139, USA. */
/* -------------------------------------------------------------------------- */
/* This script is suitable for use with Or1ksim when used with newlib. There
* are versions of this library which use a UART for input/output and a
* version which provides just output via l.nop.
*
* For explanation of the different fields, see the default simulation
* configuration file supplied with or1ksim (sim.cfg). */
/* -------------------------------------------------------------------------- */
section memory
name = "RAM"
type = unknown
ce = 0
mc = 0
baseaddr = 0x00000000
size = 0x00800000
delayr = 1
delayw = 2
end
section sim
verbose = 0
debug = 0
profile = 0
history = 0
clkcycle = 40ns /* 25MHz clock */
end
section cpu
ver = 0x12
cfg = 0x00
rev = 0x0001
superscalar = 0
hazards = 0
dependstats = 0
sbuf_len = 0
end
/* Optional sections which may be disabled on enabled, according to the precise
options in or1ksim_board.h and the version of the library selected. */
section ic
enabled = 1
nsets = 256
nways = 1
blocksize = 16
hitdelay = 20
missdelay = 20
end
section dc
enabled = 0
nsets = 512
nways = 1
blocksize = 16
load_hitdelay = 20
load_missdelay = 20
store_hitdelay = 20
store_missdelay = 20
end
section uart
enabled = 0
baseaddr = 0x90000000
channel = "xterm:"
jitter = -1 /* async behaviour */
16550 = 1
end
section debug
enabled = 0
end
/* Disabled Sections. The first one needs all its additional fields due to a
bug in Or1ksim */
section immu
enabled = 0
end
section dmmu
enabled = 0
end
section VAPI
enabled = 0
end
section dma
enabled = 0
end
section pm
enabled = 0
end
section bpb
enabled = 0
end
section ethernet
enabled = 0
end
section gpio
enabled = 0
end
section ata
enabled = 0
end
section vga
enabled = 0
end
section fb
enabled = 0
end
section kbd
enabled = 0
end
section mc
enabled = 0
end
section pic
enabled = 0
end
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