URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [powerpc/] [setjmp.S] - Rev 207
Compare with Previous | Blame | View Log
/* This is a simple version of setjmp and longjmp for the PowerPC.Ian Lance Taylor, Cygnus Support, 9 Feb 1994.Modified by Jeff Johnston, Red Hat Inc. 2 Oct 2001. */#include "ppc-asm.h"FUNC_START(setjmp)#ifdef __ALTIVEC__addi 3,3,15 # align Altivec to 16 byte boundaryrlwinm 3,3,0,0,27#elseaddi 3,3,7 # align to 8 byte boundaryrlwinm 3,3,0,0,28#endif#if __SPE__/* If we are E500, then save 64-bit registers. */evstdd 1,0(3) # offset 0evstdd 2,8(3) # offset 8evstdd 13,16(3) # offset 16evstdd 14,24(3) # offset 24evstdd 15,32(3) # offset 32evstdd 16,40(3) # offset 40evstdd 17,48(3) # offset 48evstdd 18,56(3) # offset 56evstdd 19,64(3) # offset 64evstdd 20,72(3) # offset 72evstdd 21,80(3) # offset 80evstdd 22,88(3) # offset 88evstdd 23,96(3) # offset 96evstdd 24,104(3) # offset 104evstdd 25,112(3) # offset 112evstdd 26,120(3) # offset 120evstdd 27,128(3) # offset 128evstdd 28,136(3) # offset 136evstdd 29,144(3) # offset 144evstdd 30,152(3) # offset 152evstdd 31,160(3) # offset 160/* Add 164 to r3 to account for the amount of data we juststored. Note that we are not adding 168 because the nextstore instruction uses an offset of 4. */addi 3,3,164#elsestw 1,0(3) # offset 0stwu 2,4(3) # offset 4stwu 13,4(3) # offset 8stwu 14,4(3) # offset 12stwu 15,4(3) # offset 16stwu 16,4(3) # offset 20stwu 17,4(3) # offset 24stwu 18,4(3) # offset 28stwu 19,4(3) # offset 32stwu 20,4(3) # offset 36stwu 21,4(3) # offset 40stwu 22,4(3) # offset 44stwu 23,4(3) # offset 48stwu 24,4(3) # offset 52stwu 25,4(3) # offset 56stwu 26,4(3) # offset 60stwu 27,4(3) # offset 64stwu 28,4(3) # offset 68stwu 29,4(3) # offset 72stwu 30,4(3) # offset 76stwu 31,4(3) # offset 80#endif/* From this point on until the end of this function, add 84to the offset shown if __SPE__. This difference comes fromthe fact that we save 21 64-bit registers instead of 2132-bit registers above. */mflr 4stwu 4,4(3) # offset 84mfcr 4stwu 4,4(3) # offset 88# one word pad to get floating point aligned on 8 byte boundary/* Check whether we need to save FPRs. Checking __NO_FPRS__on its own would be enough for GCC 4.1 and above, but oldercompilers only define _SOFT_FLOAT, so check both. */#if !defined (__NO_FPRS__) && !defined (_SOFT_FLOAT)stfdu 14,8(3) # offset 96stfdu 15,8(3) # offset 104stfdu 16,8(3) # offset 112stfdu 17,8(3) # offset 120stfdu 18,8(3) # offset 128stfdu 19,8(3) # offset 136stfdu 20,8(3) # offset 144stfdu 21,8(3) # offset 152stfdu 22,8(3) # offset 160stfdu 23,8(3) # offset 168stfdu 24,8(3) # offset 176stfdu 25,8(3) # offset 184stfdu 26,8(3) # offset 192stfdu 27,8(3) # offset 200stfdu 28,8(3) # offset 208stfdu 29,8(3) # offset 216stfdu 30,8(3) # offset 224stfdu 31,8(3) # offset 232#endif/* This requires a total of 21 * 4 + 18 * 8 + 4 + 4 + 4bytes == 60 * 4 bytes == 240 bytes. */#ifdef __ALTIVEC__/* save Altivec vrsave and vr20-vr31 registers */mfspr 4,256 # vrsave registerstwu 4,16(3) # offset 248addi 3,3,8stvx 20,0,3 # offset 256addi 3,3,16stvx 21,0,3 # offset 272addi 3,3,16stvx 22,0,3 # offset 288addi 3,3,16stvx 23,0,3 # offset 304addi 3,3,16stvx 24,0,3 # offset 320addi 3,3,16stvx 25,0,3 # offset 336addi 3,3,16stvx 26,0,3 # offset 352addi 3,3,16stvx 27,0,3 # offset 368addi 3,3,16stvx 28,0,3 # offset 384addi 3,3,16stvx 29,0,3 # offset 400addi 3,3,16stvx 30,0,3 # offset 416addi 3,3,16stvx 31,0,3 # offset 432/* This requires a total of 240 + 8 + 8 + 12 * 16 == 448 bytes. */#endifli 3,0blrFUNC_END(setjmp)FUNC_START(longjmp)#ifdef __ALTIVEC__addi 3,3,15 # align Altivec to 16 byte boundaryrlwinm 3,3,0,0,27#elseaddi 3,3,7 # align to 8 byte boundaryrlwinm 3,3,0,0,28#endif#if __SPE__/* If we are E500, then restore 64-bit registers. */evldd 1,0(3) # offset 0evldd 2,8(3) # offset 8evldd 13,16(3) # offset 16evldd 14,24(3) # offset 24evldd 15,32(3) # offset 32evldd 16,40(3) # offset 40evldd 17,48(3) # offset 48evldd 18,56(3) # offset 56evldd 19,64(3) # offset 64evldd 20,72(3) # offset 72evldd 21,80(3) # offset 80evldd 22,88(3) # offset 88evldd 23,96(3) # offset 96evldd 24,104(3) # offset 104evldd 25,112(3) # offset 112evldd 26,120(3) # offset 120evldd 27,128(3) # offset 128evldd 28,136(3) # offset 136evldd 29,144(3) # offset 144evldd 30,152(3) # offset 152evldd 31,160(3) # offset 160/* Add 164 to r3 to account for the amount of data we justloaded. Note that we are not adding 168 because the nextload instruction uses an offset of 4. */addi 3,3,164#elselwz 1,0(3) # offset 0lwzu 2,4(3) # offset 4lwzu 13,4(3) # offset 8lwzu 14,4(3) # offset 12lwzu 15,4(3) # offset 16lwzu 16,4(3) # offset 20lwzu 17,4(3) # offset 24lwzu 18,4(3) # offset 28lwzu 19,4(3) # offset 32lwzu 20,4(3) # offset 36lwzu 21,4(3) # offset 40lwzu 22,4(3) # offset 44lwzu 23,4(3) # offset 48lwzu 24,4(3) # offset 52lwzu 25,4(3) # offset 56lwzu 26,4(3) # offset 60lwzu 27,4(3) # offset 64lwzu 28,4(3) # offset 68lwzu 29,4(3) # offset 72lwzu 30,4(3) # offset 76lwzu 31,4(3) # offset 80#endif/* From this point on until the end of this function, add 84to the offset shown if __SPE__. This difference comes fromthe fact that we restore 21 64-bit registers instead of 2132-bit registers above. */lwzu 5,4(3) # offset 84mtlr 5lwzu 5,4(3) # offset 88mtcrf 255,5# one word pad to get floating point aligned on 8 byte boundary/* Check whether we need to restore FPRs. Checking__NO_FPRS__ on its own would be enough for GCC 4.1 andabove, but older compilers only define _SOFT_FLOAT, socheck both. */#if !defined (__NO_FPRS__) && !defined (_SOFT_FLOAT)lfdu 14,8(3) # offset 96lfdu 15,8(3) # offset 104lfdu 16,8(3) # offset 112lfdu 17,8(3) # offset 120lfdu 18,8(3) # offset 128lfdu 19,8(3) # offset 136lfdu 20,8(3) # offset 144lfdu 21,8(3) # offset 152lfdu 22,8(3) # offset 160lfdu 23,8(3) # offset 168lfdu 24,8(3) # offset 176lfdu 25,8(3) # offset 184lfdu 26,8(3) # offset 192lfdu 27,8(3) # offset 200lfdu 28,8(3) # offset 208lfdu 29,8(3) # offset 216lfdu 30,8(3) # offset 224lfdu 31,8(3) # offset 232#endif#ifdef __ALTIVEC__/* restore Altivec vrsave and v20-v31 registers */lwzu 5,16(3) # offset 248mtspr 256,5 # vrsaveaddi 3,3,8lvx 20,0,3 # offset 256addi 3,3,16lvx 21,0,3 # offset 272addi 3,3,16lvx 22,0,3 # offset 288addi 3,3,16lvx 23,0,3 # offset 304addi 3,3,16lvx 24,0,3 # offset 320addi 3,3,16lvx 25,0,3 # offset 336addi 3,3,16lvx 26,0,3 # offset 352addi 3,3,16lvx 27,0,3 # offset 368addi 3,3,16lvx 28,0,3 # offset 384addi 3,3,16lvx 29,0,3 # offset 400addi 3,3,16lvx 30,0,3 # offset 416addi 3,3,16lvx 31,0,3 # offset 432#endifmr. 3,4bclr+ 4,2li 3,1blrFUNC_END(longjmp)