OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [ld/] [testsuite/] [ld-powerpc/] [aix-gc-1-64.dd] - Rev 847

Go to most recent revision | Compare with Previous | Blame | View Log


.*


Disassembly of section \.text:

0000000010000000 <\.init_function>:
    10000000:   e8 22 00 00     ld      r1,0\(r2\)

0000000010000004 <\.fini_function>:
    10000004:   e8 22 00 08     ld      r1,8\(r2\)

0000000010000008 <\.exported_global>:
    10000008:   48 00 00 09     bl      10000010 <\.indirect2>

000000001000000c <\.indirect1>:
    1000000c:   81 08 00 04     lwz     r8,4\(r8\)

0000000010000010 <\.indirect2>:
    10000010:   81 08 00 08     lwz     r8,8\(r8\)

0000000010000014 <\.indirect3>:
    10000014:   81 08 00 0c     lwz     r8,12\(r8\)

Disassembly of section \.data:

0000000020000000 <block>:
# Pointer to indirect3.
    20000000:   20 00 00 e0     .*
    20000004:   11 22 33 44     .*

0000000020000008 <__rtinit>:
#...

0000000020000080 <exported_global>:
    20000080:   00 00 00 00     .*
    20000084:   10 00 00 08     .*
    20000088:   00 00 00 00     .*
    2000008c:   20 00 00 f8     .*
    20000090:   00 00 00 00     .*
    20000094:   00 00 00 00     .*

0000000020000098 <init_function>:
    20000098:   00 00 00 00     .*
    2000009c:   10 00 00 00     .*
    200000a0:   00 00 00 00     .*
    200000a4:   20 00 00 f8     .*
    200000a8:   00 00 00 00     .*
    200000ac:   00 00 00 00     .*

00000000200000b0 <indirect1>:
    200000b0:   00 00 00 00     .*
    200000b4:   10 00 00 0c     .*
    200000b8:   00 00 00 00     .*
    200000bc:   20 00 00 f8     .*
    200000c0:   00 00 00 00     .*
    200000c4:   00 00 00 00     .*

00000000200000c8 <fini_function>:
    200000c8:   00 00 00 00     .*
    200000cc:   10 00 00 04     .*
    200000d0:   00 00 00 00     .*
    200000d4:   20 00 00 f8     .*
    200000d8:   00 00 00 00     .*
    200000dc:   00 00 00 00     .*

00000000200000e0 <indirect3>:
    200000e0:   00 00 00 00     .*
    200000e4:   10 00 00 14     .*
    200000e8:   00 00 00 00     .*
    200000ec:   20 00 00 f8     .*
    200000f0:   00 00 00 00     .*
    200000f4:   00 00 00 00     .*

00000000200000f8 <TOC>:
    200000f8:   00 00 00 00     .*
    200000fc:   20 00 00 b0     .*

0000000020000100 <block>:
    20000100:   00 00 00 00     .*
    20000104:   20 00 00 00     .*

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.