OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-10.c] - Rev 321

Go to most recent revision | Compare with Previous | Blame | View Log

/* { dg-options "-O2 -mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */
int bar (int);
 
/* Test that code after a branch-likely does not get an unnecessary
   cache barrier.  */
 
NOMIPS16 void
foo (int n, int *x)
{
  do
    n = bar (n * 4 + 1);
  while (n);
  /* The preceding branch should be a branch likely, with the shift as
     its delay slot.  We therefore don't need a cache barrier here.  */
  x[0] = 0;
}
 
/* { dg-final { scan-assembler-not "\tcache\t" } } */
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.