OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [save-restore-5.c] - Rev 826

Compare with Previous | Blame | View Log

/* Check that we don't try to save the same register twice.  */
/* { dg-options "(-mips16) isa_rev>=1 -mgp32 -O2" } */
 
int bar (int, int, int, int);
void frob (void);
 
MIPS16 void
foo (int a1, int a2, int a3, int a4)
{
  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
		"$18", "$19", "$20", "$21", "$22", "$23", "$24",
		"$25", "$30", "$31", "memory");
  __builtin_eh_return (bar (a1, a2, a3, a4), frob);
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.