URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-7.c] - Rev 859
Go to most recent revision | Compare with Previous | Blame | View Log
/* { dg-do compile } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ /* { dg-final { scan-assembler-times "vor" 2 } } */ #include <altivec.h> /* Make sure that lvlx and lvrx are not combined into one insn and we still get a vor. */ vector unsigned char lvx_float (long off, float *p) { vector unsigned char l, r; l = (vector unsigned char) vec_lvlx (off, p); r = (vector unsigned char) vec_lvrx (off, p); return vec_or(l, r); } vector unsigned char lvxl_float (long off, float *p) { vector unsigned char l, r; l = (vector unsigned char) vec_lvlxl (off, p); r = (vector unsigned char) vec_lvrxl (off, p); return vec_or(l, r); }
Go to most recent revision | Compare with Previous | Blame | View Log