OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [gdb/] [testsuite/] [gdb.arch/] [thumb-prologue.exp] - Rev 841

Compare with Previous | Blame | View Log

# Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.

# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.

# Test ARM/Thumb prologue analyzer.

if {![istarget arm*-*]} then {
    verbose "Skipping ARM prologue tests."
    return
}

set testfile "thumb-prologue"
set srcfile ${testfile}.c
set binfile ${objdir}/${subdir}/${testfile}

# Don't use "debug", so that we don't have line information for the assembly
# fragments.
if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {"additional_flags=-mthumb"}] != "" } {
    untested "ARM prologue tests"
    return -1
}


gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${binfile}

#
# Run to `main' where we begin our tests.
#

if ![runto_main] then {
    untested "ARM prologue tests"
    return -1
}

# Testcase for TPCS prologue.

gdb_breakpoint "* *(int *)tpcs_offset + (int) &tpcs_frame_1"
gdb_test "continue" "Breakpoint .*, $hex in tpcs_frame_1 \\(\\)" \
    "continue to TPCS"

gdb_test "backtrace 10" \
        "#0\[ \t\]*$hex in tpcs_frame_1 .*\r\n#1\[ \t\]*$hex in tpcs_frame .*\r\n#2\[ \t\]*$hex in main.*" \
        "backtrace in TPCS"

gdb_test "info frame" \
        ".*Saved registers:.*r7 at.*r10 at.*r11 at.*lr at.*" \
        "saved registers in TPCS"

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.