OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [gdb/] [testsuite/] [gdb.cell/] [ptype.exp] - Rev 841

Compare with Previous | Blame | View Log

# Copyright 2009 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.
#
# Contributed by Markus Deuling <deuling@de.ibm.com>.
#
# Testsuite for Cell Broadband Engine combined debugger
# Test ptype and print/set of SPU-side registers.

load_lib cell.exp

set ppu_file "break"
set ppu_src ${srcdir}/${subdir}/${ppu_file}.c
set ppu_bin ${objdir}/${subdir}/${ppu_file}
set spu_file "break-spu"
set spu_src ${srcdir}/${subdir}/${spu_file}.c
set spu_bin ${objdir}/${subdir}/${spu_file}

if {[skip_cell_tests]} {
    return 0
}

# Compile SPU binary.
if { [gdb_compile_cell_spu $spu_src $spu_bin executable {debug}]  != "" } {
  unsupported "Compiling spu binary failed."
  return -1
}
# Compile PPU binary.
if { [gdb_cell_embedspu $spu_bin $spu_bin-embed.o {debug}]  != "" } {
  unsupported "Embedding spu binary failed."
  return -1
}
if { [gdb_compile_cell_ppu [list $ppu_src $spu_bin-embed.o] $ppu_bin executable {debug}] != "" } {
  unsupported "Compiling ppu binary failed."
  return -1
}

if [get_compiler_info ${ppu_bin}] {
  return -1
}

gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${ppu_bin}

if ![runto_main] then {
  fail "Can't run to main"
  return 0
}

# Continue to SPU
cont_spu_main

gdb_test "info registers r2"  \
         "r2.*\{uint128 =.*v2_int64 =.*v4_int32 =.*v8_int16 =.*v16_int8 =.*v2_double =.*v4_float =.*\}.*" \
         "info registers r2"

for {set check_reg 10} {$check_reg < 12} {incr check_reg} {
  gdb_test "print \$r$check_reg\.v4_int32" \
           ".*= \{.*,.*,.*,.*\}" \
           "print \$r$check_reg\.v4_int32"

  gdb_test "ptype \$r$check_reg" \
           "type = union __spu_builtin_type_vec128.*\{.*int128_t uint128.* \
            int64_t v2_int64.*int32_t v4_int32.*int16_t v8_int16.* \
            int8_t v16_int8.*double v2_double.*float v4_float.*\}" \
           "ptype \$r$check_reg"

  gdb_test "set \$r$check_reg\.v4_int32 = {1,2,3,4}" \
           "" \
           "set \$r$check_reg\.v4_int32 = {1,2,3,4}"

  gdb_test "print \$r$check_reg\.v4_int32" \
           ".*= \{.*1, 2, 3, 4.*\}" \
           "print \$r$check_reg\.v4_int32"

  gdb_test "print \$r$check_reg.v4_int32\[0\]" \
           ".*= 1.*" \
           "print \$r$check_reg.v4_int32\[0\]"

  gdb_test "print \$r$check_reg.v4_int32\[1\]" \
           ".*= 2.*" \
           "print \$r$check_reg.v4_int32\[1\]"

  gdb_test "print \$r$check_reg.v4_int32\[2\]" \
           ".*= 3.*" \
           "print \$r$check_reg.v4_int32\[2\]"

  gdb_test "print \$r$check_reg.v4_int32\[3\]" \
           ".*= 4.*" \
           "print \$r$check_reg.v4_int32\[3\]"

  gdb_test "print \$r$check_reg.v4_int32\[4\]" \
           "no such vector element" \
           "print \$r$check_reg.v4_int32\[4\]"

  # Set single array elements to other values and check the results.
  gdb_test "set \$r$check_reg\.v4_int32\[0\] = 5" \
           "" \
           "set \$r$check_reg\.v4_int32\[0\] = 5"
  gdb_test "print \$r$check_reg.v4_int32\[0\]" \
           ".*= 5.*" \
           "print \$r$check_reg.v4_int32\[0\]"

  gdb_test "set \$r$check_reg\.v4_int32\[1\] = 6" \
           "" \
           "set \$r$check_reg\.v4_int32\[1\] = 6"
  gdb_test "print \$r$check_reg.v4_int32\[1\]" \
           ".*= 6.*" \
           "print \$r$check_reg.v4_int32\[1\]"

  gdb_test "set \$r$check_reg\.v4_int32\[2\] = 7" \
           "" \
           "set \$r$check_reg\.v4_int32\[2\] = 7"
  gdb_test "print \$r$check_reg.v4_int32\[2\]" \
           ".*= 7.*" \
           "print \$r$check_reg.v4_int32\[2\]"

  gdb_test "set \$r$check_reg\.v4_int32\[3\] = 8" \
           "" \
           "set \$r$check_reg\.v4_int32\[3\] = 8"
  gdb_test "print \$r$check_reg.v4_int32\[3\]" \
           ".*= 8.*" \
           "print \$r$check_reg.v4_int32\[3\]"

  # Now there should be {5, 6, 7, 8} in that array.
  gdb_test "print \$r$check_reg\.v4_int32" \
           ".*= \{.*5, 6, 7, 8.*\}" \
           "print \$r$check_reg\.v4_int32"
}

gdb_exit
return 0

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.