OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [configure.tgt] - Rev 853

Go to most recent revision | Compare with Previous | Blame | View Log

dnl Note that this file is intended to be included at the m4 level and not
dnl the shell level, so use sinclude(...) to pull it in.

# WHEN ADDING ENTRIES TO THIS MATRIX:

# Make sure that the left side always has two dashes.  Otherwise you
# can get spurious matches.  Even for unambiguous cases, do this as a
# convention, else the table becomes a real mess to understand and
# maintain.

dnl glue to avoid code duplication at top level
m4_ifndef([SIM_ARCH], [AC_DEFUN([SIM_ARCH],[sim_arch=$1])])

sim_testsuite=no
sim_common=yes
sim_igen=no
sim_arch=
case "${target}" in
   arm*-*-* | thumb*-*-* | strongarm*-*-* | xscale-*-*)
       SIM_ARCH(arm)
       sim_testsuite=yes
       ;;
   avr*-*-*)
       SIM_ARCH(avr)
       ;;
   cr16*-*-*)
       SIM_ARCH(cr16)
       sim_testsuite=yes
       ;;
   cris-*-* | crisv32-*-*)
       SIM_ARCH(cris)
       sim_testsuite=yes
       ;;
   d10v-*-*)
       SIM_ARCH(d10v)
       ;;
   frv-*-*)
       SIM_ARCH(frv)
       sim_testsuite=yes
       ;;
   h8300*-*-*)
       SIM_ARCH(h8300)
       sim_testsuite=yes
       ;;
   iq2000-*-*)
       SIM_ARCH(iq2000)
       sim_testsuite=yes
       ;;
   lm32-*-*)
       SIM_ARCH(lm32)
       sim_testsuite=yes
       ;;
   m32c-*-*)
       SIM_ARCH(m32c)
       ;;
   m32r-*-*)
       SIM_ARCH(m32r)
       sim_testsuite=yes
       ;;
   m68hc11-*-*|m6811-*-*)
       SIM_ARCH(m68hc11)
       sim_testsuite=yes
       ;;
   mcore-*-*)
       SIM_ARCH(mcore)
       sim_testsuite=yes
       ;;
   microblaze-*-*)
       SIM_ARCH(microblaze)
       sim_testsuite=yes
       ;;
   mips*-*-*)
       SIM_ARCH(mips)
       sim_testsuite=yes
       sim_igen=yes
       ;;
   mn10300*-*-*)
       SIM_ARCH(mn10300)
       sim_igen=yes
       ;;
   moxie-*-*)
       SIM_ARCH(moxie)
       sim_testsuite=yes
       ;;
   or32-*-*)
       SIM_ARCH(or32)
       ;;
   rx-*-*)
       SIM_ARCH(rx)
       ;;
   sh64*-*-*)
       SIM_ARCH(sh64)
       sim_testsuite=yes
       ;;
   sh*-*-*)
       SIM_ARCH(sh)
       sim_testsuite=yes
       ;;
   sparc-*-rtems*|sparc-*-elf*)
       SIM_ARCH(erc32)
       sim_testsuite=yes
       ;;
   powerpc*-*-*)
       SIM_ARCH(ppc)
       ;;
   v850*-*-*)
       SIM_ARCH(v850)
       sim_igen=yes
       sim_testsuite=yes
       ;;
   *)
       # No simulator subdir, so the subdir "common" isn't needed.
       sim_common=no
       ;;
esac
AC_SUBST(sim_arch)

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.