OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [moxie/] [ChangeLog] - Rev 855

Go to most recent revision | Compare with Previous | Blame | View Log

2010-04-14  Mike Frysinger  <vapier@gentoo.org>

        * interp.c (sim_write): Add const to buffer arg.

2010-02-27  Jan Kratochvil  <jan.kratochvil@redhat.com>

        * interp.c (sim_create_inferior): Fix crashes on zero PROG_BFD or ARGV.

2010-02-03  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): nop is 0x0f, and 0x00 is an illegal
        instruction.

2010-01-13  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_open): Add period to end of sentence in comment.

2010-01-13  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_open): Initialize the SIM_DESC object properly
        with sim_config() and sim_post_argv_init().

2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

        * configure: Regenerate.

2009-09-10  Anthony Green  <green@moxielogic.com>

        * Makefile.in (install-dtb): New target.
        (moxie-gdb.dtb): New target.
        (SIM_CFLAGS): Define DTB macro on command line.
        (SIM_OBJS): Use common infrastructire.
        (dtbdir): Define install location for dtb file.

        * sim-main.h: New file.
        * moxie-gdb.dts: New file.
        * configure.ac: Check for dtc.  Install dtb file.  Remove some old
        cruft.
        * configure: Regenerate.
        * interp.c: Many changes to use common memory infrastructure.
        (load_dtb): New function.
        (sim_create_inferior): Call it.

2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

        * config.in: Regenerate.
        * configure: Likewise.

        * configure: Regenerate.

2009-07-31  Anthony Green  <green@moxielogic.com>

        * interp.c: Increase simulated memory to 16MB.
        (sim_resume): Tweak swi system calls to support new ABI (up to 5
        args in regs).  Also simluate proper exception processing for
        Linux system calls.

2009-07-30  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add system call software interrupt support.

2009-06-11  Anthony Green  <green@moxielogic.com>

        * interp.c (INST2OFFSET): Define.
        (sim_resume): Support new PC relative branch instructions.

2009-05-09  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add missing breaks in switch.

2008-10-03  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add support for ldo.b, sto.b, ldo.s, sto.s.

2008-09-10  Anthony Green  <green@moxielogic.com>

        * interp.c (NUM_SPRO_SREGS): New.
        (struct moxie_regset): Add sregs.
        (set_initial_gprs): Initialize sregs.
        (sim_resume): Add gsr and ssr support.

2008-09-04  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add inc and dec instructions.

2008-09-04  Anthony Green  <green@moxielogic.com>

        * interp.c (struct moxie_regset): Use an unsigned long long to keep
        track of instruction trace counts.
        * interp.c (sim_resume): Ditto.
        (sim_info): Ditto.

2008-08-22  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Remove debugging code.

2008-08-20  Anthony Green  <green@moxielogic.com>

        * interp.c (TRACE): Add new tracing infrastructure.
        (sim_resume): Use it.
        (reg_names): Add new registers.
        (NUM_MOXIE_REGS): New registers.
        (PC_REGNO): New registers.
        (sim_resume): New instruction encodings.

2008-08-16  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add SYS_read, and fix SYS_open and SYS_write.
        (convert_target_flags): New function.

2008-08-08  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add SYS_open and SYS_write system call support.

2008-08-04  Anthony Green  <green@moxielogic.com>

        * Makefile.in (SIM_EXTRA_LIBS): Add -lz.

2008-08-04  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_create_inferior): Set argc & argv in the target.

2008-04-12  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add brk.

2008-04-10  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add static chain pointer to call frame.

2008-03-24  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add missing breaks.
        (sim_resume): Fix neg implementation.

2008-03-23  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_load): Don't require a .bss section.

2008-03-21  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add swi, and, lshr, ashl, sub.l, neg, or,
        not, ashr, xor.

2008-03-20  Anthony Green  <green@moxielogic.com>

        * interp.c (struct moxie_regset): Add condition code, cc.
        (CC_GT, CC_LT, CC_EQ, CC_GTU, CC_LTU): Define.
        (sim_resume): Add jmpa, jsr, cmp, beq, bne, blt, bgt, bltu, bgtu,
        bge, ble, bgeu, and bleu.
        (rbat, rsat, wbat, wsat): New functions.
        (sim_resume): Add ld.b, lda.b, ldi.b, ld.s, lda.s, ldi.s, st.b,
        sta.b, st.s, sta.s, jmp.

2008-03-19  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add ld.l, st.l, lda.l, sta.l.
        jsra should set $fp == $sp.
        Fix jsra and ret semantics.

2008-03-18  Anthony Green  <green@moxielogic.com>

        * interp.c (sim_resume): Add push, pop and add.l.

2008-03-16  Anthony Green  <green@moxielogic.com>

        * interp.c (EXTRACT_WORD): Define.
        (rlat): Use EXTRACT_WORD.
        (sim_resume): Add jsra and ret.

2008-02-22  Anthony Green  <green@moxielogic.com>

        * interp.c (reg_names): Define.
        (sim_resume): Use reg_names.

2008-02-21  Anthony Green  <green@moxielogic.com>

        * config.in, configure, configure.ac, interp.c, Makefile.in,
        sysdep.h: Created.

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.