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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [mdasaccs.cgs] - Rev 816
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# frv testcase for mdasaccs $ACC40Si,$ACC40Sk# mach: fr400.include "testutils.inc"start.global mdasaccsmdasaccs:set_accg_immed 0,accg0set_acc_immed 0x00000000,acc0set_accg_immed 0,accg1set_acc_immed 0x00000000,acc1set_accg_immed 0,accg2set_acc_immed 0xdead0000,acc2set_accg_immed 0,accg3set_acc_immed 0x0000beef,acc3mdasaccs acc0,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x0000,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x0000,acc1test_accg_immed 0,accg2test_acc_limmed 0xdead,0xbeef,acc2test_accg_immed 0,accg3test_acc_limmed 0xdeac,0x4111,acc3set_accg_immed 0,accg0set_acc_immed 0x0000dead,acc0set_accg_immed 0,accg1set_acc_immed 0xbeef0000,acc1set_accg_immed 0,accg2set_acc_immed 0x12345678,acc2set_accg_immed 0,accg3set_acc_immed 0x11111111,acc3mdasaccs acc0,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0xbeef,0xdead,acc0test_accg_immed 0xff,accg1test_acc_limmed 0x4111,0xdead,acc1test_accg_immed 0,accg2test_acc_limmed 0x2345,0x6789,acc2test_accg_immed 0,accg3test_acc_limmed 0x0123,0x4567,acc3set_accg_immed 0,accg0set_acc_immed 0x12345678,acc0set_accg_immed 0,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0,accg2set_acc_immed 0x12345678,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3mdasaccs acc0,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 1,accg0test_acc_limmed 0x1234,0x5677,acc0test_accg_immed 0xff,accg1test_acc_limmed 0x1234,0x5679,acc1test_accg_immed 0,accg2test_acc_limmed 0x1234,0x5677,acc2test_accg_immed 0,accg3test_acc_limmed 0x1234,0x5679,acc3set_spr_immed 0,msr0set_accg_immed 0x7f,accg0set_acc_immed 0xfffe7ffe,acc0set_accg_immed 0x0,accg1set_acc_immed 0x00020001,acc1set_accg_immed 0x80,accg2set_acc_immed 0x00000001,acc2set_accg_immed 0xff,accg3set_acc_immed 0xfffffffe,acc3mdasaccs acc0,acc0test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt settest_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xfffc,0x7ffd,acc1test_accg_immed 0x80,accg2test_acc_limmed 0x0000,0x0000,acc2test_accg_immed 0x80,accg3test_acc_limmed 0x0000,0x0003,acc3set_spr_immed 0,msr0set_accg_immed 0,accg0set_acc_immed 0x00000001,acc0set_accg_immed 0,accg1set_acc_immed 0x00000001,acc1set_accg_immed 0,accg2set_acc_immed 0x00000001,acc2set_accg_immed 0x7f,accg3set_acc_immed 0xffffffff,acc3mdasaccs acc0,acc0test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x0002,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x0000,acc1test_accg_immed 0x7f,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0x80,accg3test_acc_limmed 0x0000,0x0002,acc3pass
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