Subversion Repositories openrisc_me

#!/bin/sh
nLint \
../../rtl/verilog/or1200_alu.v \
../../rtl/verilog/or1200_amultp2_32x32.v \
../../rtl/verilog/or1200_cfgr.v \
../../rtl/verilog/or1200_cpu.v \
../../rtl/verilog/or1200_ctrl.v \
../../rtl/verilog/or1200_dc_fsm.v \
../../rtl/verilog/or1200_dc_ram.v \
../../rtl/verilog/or1200_dc_tag.v \
../../rtl/verilog/or1200_dc_top.v \
../../rtl/verilog/or1200_defines.v \
../../rtl/verilog/or1200_dmmu_tlb.v \
../../rtl/verilog/or1200_dmmu_top.v \
../../rtl/verilog/or1200_dpram_32x32.v \
../../rtl/verilog/or1200_du.v \
../../rtl/verilog/or1200_except.v \
../../rtl/verilog/or1200_freeze.v \
../../rtl/verilog/or1200_genpc.v \
../../rtl/verilog/or1200_gmultp2_32x32.v \
../../rtl/verilog/or1200_ic_fsm.v \
../../rtl/verilog/or1200_ic_ram.v \
../../rtl/verilog/or1200_ic_tag.v \
../../rtl/verilog/or1200_ic_top.v \
../../rtl/verilog/or1200_if.v \
../../rtl/verilog/or1200_immu_tlb.v \
../../rtl/verilog/or1200_immu_top.v \
../../rtl/verilog/or1200_lsu.v \
../../rtl/verilog/or1200_mem2reg.v \
../../rtl/verilog/or1200_mult_mac.v \
../../rtl/verilog/or1200_operandmuxes.v \
../../rtl/verilog/or1200_pic.v \
../../rtl/verilog/or1200_pm.v \
../../rtl/verilog/or1200_reg2mem.v \
../../rtl/verilog/or1200_rf.v \
../../rtl/verilog/or1200_rfram_generic.v \
../../rtl/verilog/or1200_sb.v \
../../rtl/verilog/or1200_sb_fifo.v \
../../rtl/verilog/or1200_spram_1024x32.v \
../../rtl/verilog/or1200_spram_1024x8.v \
../../rtl/verilog/or1200_spram_2048x32.v \
../../rtl/verilog/or1200_spram_2048x8.v \
../../rtl/verilog/or1200_spram_256x21.v \
../../rtl/verilog/or1200_spram_512x20.v \
../../rtl/verilog/or1200_spram_64x14.v \
../../rtl/verilog/or1200_spram_64x22.v \
../../rtl/verilog/or1200_spram_64x24.v \
../../rtl/verilog/or1200_sprs.v \
../../rtl/verilog/or1200_top.v \
../../rtl/verilog/or1200_tpram_32x32.v \
../../rtl/verilog/or1200_tt.v \
../../rtl/verilog/or1200_wb_biu.v \
../../rtl/verilog/or1200_wbmux.v \
../../rtl/verilog/or1200_xcv_ram32x8d.v > ../log/nlint.log && \
mv nLintLog ../log &