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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_iwb_biu.v] - Rev 836
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's WISHBONE BIU //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://opencores.org/project,or1k //// //// //// //// Description //// //// Implements WISHBONE interface //// //// //// //// To Do: //// //// - if biu_cyc/stb are deasserted and wb_ack_i is asserted //// //// and this happens even before aborted_r is asssrted, //// //// wb_ack_i will be delivered even though transfer is //// //// internally considered already aborted. However most //// //// wb_ack_i are externally registered and delayed. Normally //// //// this shouldn't cause any problems. //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // $Log: or1200_iwb_biu.v,v $ // Revision 2.0 2010/06/30 11:00:00 ORSoC // Major update: // This module is obsolete. // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_iwb_biu(); // THIS MODULE IS OBSOLETE !!! // COMPLETELY REWRITTEN or1200_wb_biu.v IS USED INSTEAD !!! endmodule
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