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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Rev 357
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's register file inside CPU //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/project,or1k //// //// //// //// Description //// //// Instantiation of register file memories //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // $Log: or1200_rf.v,v $ // Revision 2.0 2010/06/30 11:00:00 ORSoC // Minor update: // Bugs fixed, coding style changed. // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_rf( // Clock and reset clk, rst, // Write i/f cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe, // Read i/f id_freeze, addra, addrb, dataa, datab, rda, rdb, // Debug spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read ); parameter dw = `OR1200_OPERAND_WIDTH; parameter aw = `OR1200_REGFILE_ADDR_WIDTH; // // I/O // // // Clock and reset // input clk; input rst; // // Write i/f // input cy_we_i; output cy_we_o; input supv; input wb_freeze; input [aw-1:0] addrw; input [dw-1:0] dataw; input we; input flushpipe; // // Read i/f // input id_freeze; input [aw-1:0] addra; input [aw-1:0] addrb; output [dw-1:0] dataa; output [dw-1:0] datab; input rda; input rdb; // // SPR access for debugging purposes // input spr_cs; input spr_write; input [31:0] spr_addr; input [31:0] spr_dat_i; output [31:0] spr_dat_o; input du_read; // // Internal wires and regs // wire [dw-1:0] from_rfa; wire [dw-1:0] from_rfb; wire [aw-1:0] rf_addra; wire [aw-1:0] rf_addrw; wire [dw-1:0] rf_dataw; wire rf_we; wire spr_valid; wire rf_ena; wire rf_enb; reg rf_we_allow; // Logic to restore output on RFA after debug unit has read out via SPR if. // Problem was that the incorrect output would be on RFA after debug unit // had read out - this is bad if that output is relied upon by execute // stage for next instruction. We simply save the last address for rf A and // and re-read it whenever the SPR select goes low, so we must remember // the last address and generate a signal for falling edge of SPR cs. // -- Julius // Detect falling edge of SPR select reg spr_du_cs; wire spr_cs_fe; // Track RF A's address each time it's enabled reg [aw-1:0] addra_last; always @(posedge clk) if (rf_ena & !(spr_cs_fe | (du_read & spr_cs))) addra_last <= addra; always @(posedge clk) spr_du_cs <= spr_cs & du_read; assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read); // // SPR access is valid when spr_cs is asserted and // SPR address matches GPR addresses // assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF); // // SPR data output is always from RF A // assign spr_dat_o = from_rfa; // // Operand A comes from RF or from saved A register // assign dataa = from_rfa; // // Operand B comes from RF or from saved B register // assign datab = from_rfb; // // RF A read address is either from SPRS or normal from CPU control // assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : spr_cs_fe ? addra_last : addra; // // RF write address is either from SPRS or normal from CPU control // assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw; // // RF write data is either from SPRS or normal from CPU datapath // assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; // // RF write enable is either from SPRS or normal from CPU control // always @(posedge rst or posedge clk) if (rst) rf_we_allow <= 1'b1; else if (~wb_freeze) rf_we_allow <= ~flushpipe; //assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw)); assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow; //assign cy_we_o = cy_we_i && rf_we; assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow; // // CS RF A asserted when instruction reads operand A and ID stage // is not stalled // //assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe; // probably works with fixed binutils // assign rf_ena = 1'b1; // does not work with single-stepping //assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils // // CS RF B asserted when instruction reads operand B and ID stage // is not stalled // //assign rf_enb = rdb & ~id_freeze | spr_valid; assign rf_enb = rdb & ~id_freeze; // assign rf_enb = 1'b1; //assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils `ifdef OR1200_RFRAM_TWOPORT // // Instantiation of register file two-port RAM A // or1200_tpram_32x32 rf_a( // Port A .clk_a(clk), .rst_a(rst), .ce_a(rf_ena), .we_a(1'b0), .oe_a(1'b1), .addr_a(rf_addra), .di_a(32'h0000_0000), .do_a(from_rfa), // Port B .clk_b(clk), .rst_b(rst), .ce_b(rf_we), .we_b(rf_we), .oe_b(1'b0), .addr_b(rf_addrw), .di_b(rf_dataw), .do_b() ); // // Instantiation of register file two-port RAM B // or1200_tpram_32x32 rf_b( // Port A .clk_a(clk), .rst_a(rst), .ce_a(rf_enb), .we_a(1'b0), .oe_a(1'b1), .addr_a(addrb), .di_a(32'h0000_0000), .do_a(from_rfb), // Port B .clk_b(clk), .rst_b(rst), .ce_b(rf_we), .we_b(rf_we), .oe_b(1'b0), .addr_b(rf_addrw), .di_b(rf_dataw), .do_b() ); `else `ifdef OR1200_RFRAM_DUALPORT // // Instantiation of register file two-port RAM A // or1200_dpram # ( .aw(5), .dw(32) ) rf_a ( // Port A .clk_a(clk), .ce_a(rf_ena), .addr_a(rf_addra), .do_a(from_rfa), // Port B .clk_b(clk), .ce_b(rf_we), .we_b(rf_we), .addr_b(rf_addrw), .di_b(rf_dataw) ); // // Instantiation of register file two-port RAM B // or1200_dpram # ( .aw(5), .dw(32) ) rf_b ( // Port A .clk_a(clk), .ce_a(rf_enb), .addr_a(addrb), .do_a(from_rfb), // Port B .clk_b(clk), .ce_b(rf_we), .we_b(rf_we), .addr_b(rf_addrw), .di_b(rf_dataw) ); `else `ifdef OR1200_RFRAM_GENERIC // // Instantiation of generic (flip-flop based) register file // or1200_rfram_generic rf_a( // Clock and reset .clk(clk), .rst(rst), // Port A .ce_a(rf_ena), .addr_a(rf_addra), .do_a(from_rfa), // Port B .ce_b(rf_enb), .addr_b(addrb), .do_b(from_rfb), // Port W .ce_w(rf_we), .we_w(rf_we), .addr_w(rf_addrw), .di_w(rf_dataw) ); `else // // RFRAM type not specified // initial begin $display("Define RFRAM type."); $finish; end `endif `endif `endif endmodule
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