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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.cxf] - Rev 393
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>flash</name><vendor>Actel</vendor><library>work</library><version>2.0</version><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>flash.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="1"><name>flash.gen</name><userFileType>GEN</userFileType></file><file fileid="2"><name>flash.log</name><userFileType>LOG</userFileType></file><file fileid="3"><name>flash.ufc</name><userFileType>Other</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="4"><name>flash.mem</name><userFileType>MEM</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel><category>FlashROM</category><f
unction>FlashROM</function><variation>FlashROM</variation><vendor>Actel</vendor><version>2.0</version><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ADDR</name><direction>in</direction><left>6</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>DOUT</name><direction>out</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
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