OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.gen] - Rev 2

Compare with Previous | Blame | View Log

Version:8.5.0.34
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_FROM
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS8X8M2
SMARTGEN_PACKAGE:pq208
AGENIII_IS_SUBPROJECT_LIBERO:T
MEMFILE:flash.mem
UFCFILE:flash.ufc

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.