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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.gen] - Rev 167

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Version:8.5.0.34
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_FROM
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS8X8M2
SMARTGEN_PACKAGE:pq208
AGENIII_IS_SUBPROJECT_LIBERO:T
MEMFILE:flash.mem
UFCFILE:flash.ufc

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