OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [smartgen.aws] - Rev 146

Go to most recent revision | Compare with Previous | Blame | View Log

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="T"/></reports><subproject libero="T"/><hdltype>Verilog</hdltype><componentInstances/><component name="flash::work"/><device die="IS8X8M2" family="ProASIC3" package="pq208"/><SmartGen version="8.0"/></workspace>

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.