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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-edge.cfg] - Rev 352
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/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC
Copyright (C) 2001, Marko Mlinar <markom@opencores.org>
Copyright (C) 2010 Embecosm Limited
Contributor Marko Mlinar <markom@opencores.org>
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "FLASH"
ce = 0
mc = 0
baseaddr = 0xf0000000
size = 0x00200000
delayr = 10
delayw = -1
end
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "RAM"
ce = 1
mc = 0
baseaddr = 0x00000000
size = 0x00200000
delayr = 2
delayw = 4
end
section immu
enabled = 1
nsets = 64
nways = 1
ustates = 2
pagesize = 8192
end
section dmmu
enabled = 1
nsets = 64
nways = 1
ustates = 2
pagesize = 8192
end
section ic
enabled = 1
nsets = 256
nways = 1
ustates = 2
blocksize = 16
end
section dc
enabled = 1
nsets = 256
nways = 1
ustates = 2
blocksize = 16
end
section cpu
ver = 0x12
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 0
dependstats = 0
end
section bpb
enabled = 0
btic = 0
end
section debug
/* enabled = 1
rsp_enabled = 1
rsp_port = 51000*/
end
section sim
debug = 0
profile = 0
prof_fn = "sim.profile"
exe_log = 0
exe_log_type = software
exe_log_fn = "executed.log"
end
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
section dma
baseaddr = 0xB8000000
irq = 4
end
section ethernet
enabled = 0
baseaddr = 0x92000000
irq = 4
rtx_type = 0
end
section VAPI
enabled = 0
server_port = 9998
end
section fb
enabled = 1
baseaddr = 0x97000000
refresh_rate = 10000
filename = "primary"
end
section kbd
enabled = 0
end
section pic
enabled = 1
edge_trigger = 1
end
section generic
enabled = 1
baseaddr = 0x98000000
size = 8
end
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