URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [acv-uart.cfg] - Rev 339
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section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "FLASH"
ce = 0
baseaddr = 0xf0000000
size = 0x00200000
delayr = 1
delayw = -1
end
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "RAM"
ce = 1
baseaddr = 0x00000000
size = 0x00200000
delayr = 1
delayw = 1
end
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
end
section cpu
ver = 0x12
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 0
dependstats = 0
end
section sim
debug = 4
verbose = 1
exe_log = 1
exe_log_fn = "executed.log"
end
section uart
baseaddr = 0x9c000000
jitter = -1 /* async behaviour */
16550 = 1
irq = 19
vapi_id = 0x100
end
section VAPI
enabled = 1
log_enabled = 1
hide_device_id = 1
vapi_log_fn = "vapi.log"
server_port = 9100
end
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