URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [inst-set-test.exp] - Rev 112
Go to most recent revision | Compare with Previous | Blame | View Log
# inst-set-test.exp. Tests of ORBIS32 instruction set
# Copyright (C) 2010 Embecosm Limited
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
# This file is part of OpenRISC 1000 Architectural Simulator.
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 3 of the License, or (at your option)
# any later version.
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
# You should have received a copy of the GNU General Public License along
# with this program. If not, see <http:#www.gnu.org/licenses/>. */
# -----------------------------------------------------------------------------
# This code is commented throughout for use with Doxygen.
# -----------------------------------------------------------------------------
# Run the l.lws test
run_or1ksim "lws-test" \
[list "!l.lws" \
" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
" l.lws r4,0(r5): r4=0x00000000: OK" \
" l.lws r4,0(r5): r4=0x7fffffff: OK" \
" l.lws r4,0(r5): r4=0x80000000: OK" \
" l.lws r4,0(r5): r4=0xffffffff: OK" \
" l.lws r4,0(r5): r4=0x00000000: OK" \
" l.lws r4,0(r5): r4=0x7fffffff: OK" \
" l.lws r4,0(r5): r4=0x80000000: OK" \
" l.lws r4,0(r5): r4=0xffffffff: OK" \
" l.lws r4,0(r5): r4=0xdeadbeef: OK" \
" l.lws r4,0(r5): r4=0x00000000: OK" \
" l.lws r4,0(r5): r4=0x7fffffff: OK" \
" l.lws r4,0(r5): r4=0x80000000: OK" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-lws-test"
# Run the l.div and l.divu test
run_or1ksim "lws-test" \
[list "!l.div" \
"! RANGE exception" \
" - caused by: report(0xe0853309);" \
"! - SR value: report(0x00008601);" \
" 1 / 0 (with error) carry flag set: TRUE" \
"!l.divu" \
"! RANGE exception" \
" - caused by: report(0xe085330a);" \
"! - SR value: report(0x00008601);" \
" 1 / 0 (with error) carry flag set: TRUE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-div-test"
# Run the l.add, l.addc, l.addi and l.addic tests
run_or1ksim "lws-test" \
[list "!l.add" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x3fffffff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xc0000000 + 0xc0000000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! OVE flag set" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009a01);" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009e01);" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! OVE flag cleared" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-add-test"
Go to most recent revision | Compare with Previous | Blame | View Log