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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [reset_buffer.v] - Rev 408
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`timescale 1 ns/100 ps // Version: 8.6 8.6.0.34 module reset_buffer(GL,CLK); output GL; input CLK; wire CLKP, GND; GND GND_1_net(.Y(GND)); PLLINT pllint1(.A(CLK), .Y(CLKP)); CLKDLY Inst1(.CLK(CLKP), .GL(GL), .DLYGL0(GND), .DLYGL1(GND), .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)); endmodule