URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Rev 502
Go to most recent revision | Compare with Previous | Blame | View Log
/* * * Clock, reset generation unit * * Implements clock generation according to design defines * */ ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `include "timescale.v" `include "orpsoc-defines.v" `include "synthesis-defines.v" module clkgen ( // Main clocks in, depending on board sys_clk_pad_i, // Wishbone clock and reset out wb_clk_o, wb_rst_o, // JTAG clock `ifdef JTAG_DEBUG tck_pad_i, dbg_tck_o, `endif // Main memory clocks `ifdef VERSATILE_SDRAM sdram_clk_o, sdram_rst_o, `endif // Peripheral clocks `ifdef ETH_CLK eth_clk_pad_i, eth_clk_o, eth_rst_o, `endif `ifdef USB_CLK usb_clk_o, `endif // Asynchronous, active low reset in rst_n_pad_i ); input sys_clk_pad_i; output wb_rst_o; output wb_clk_o; `ifdef JTAG_DEBUG input tck_pad_i; output dbg_tck_o; `endif `ifdef VERSATILE_SDRAM output sdram_clk_o; output sdram_rst_o; `endif `ifdef ETH_CLK input eth_clk_pad_i; output eth_clk_o; output eth_rst_o; `endif `ifdef USB_CLK output usb_clk_o; `endif // Asynchronous, active low reset (pushbutton, typically) input rst_n_pad_i; // First, deal with the asychronous reset wire async_rst; wire async_rst_n; reset_buffer reset_gbuf ( .GL(async_rst_n), .CLK(rst_n_pad_i) ); // Everyone likes active-high reset signals... assign async_rst = ~async_rst_n; `ifdef JTAG_DEBUG gbuf dbg_tck_gbuf ( .CLK(tck_pad_i), .GL(dbg_tck_o) ); `endif // // Declare synchronous reset wires here // // An active-low synchronous reset signal (usually a PLL lock signal) wire sync_rst_n; // An active-low synchronous reset from ethernet PLL wire sync_eth_rst_n; `ifdef ACTEL_PLL `ifdef SYNTHESIS wire pll_lock; wire eth_pll_lock; `ifdef PLL_XTAL64_WB36 pll_xtal64_wb36 `endif `ifdef PLL_XTAL64_WB32 pll_xtal64_wb32 `endif `ifdef PLL_XTAL64_WB30 pll_xtal64_wb30 `endif `ifdef PLL_XTAL64_WB24 pll_xtal64_wb24 `endif `ifdef PLL_XTAL64_WB20 pll_xtal64_wb20 `endif `ifdef PLL_XTAL64_WB18 pll_xtal64_wb18 `endif `ifdef PLL_XTAL64_WB16 pll_xtal64_wb16 `endif `ifdef PLL_XTAL25_WB24 pll_xtal25_wb24 `endif `ifdef PLL_XTAL25_WB20 pll_xtal25_wb20 `endif pll0 ( .POWERDOWN(1'b1), .CLKA(sys_clk_pad_i), .LOCK(pll_lock), `ifdef VERSATILE_SDRAM .GLA(sdram_clk_o), `else .GLA(), `endif .GLB(wb_clk_o), `ifdef USB_CLK .GLC(usb_clk_o) `else .GLC() `endif ); assign sync_rst_n = pll_lock; `ifdef ETH_CLK `ifdef ETH_CLK_PLL eth_pll eth_pll0 ( .POWERDOWN(1'b1), .CLKA(eth_clk_pad_i), .LOCK(eth_pll_lock), .GLA(eth_clk_o) ); `else // Just instantiate global buffer for incoming ethernet clock gbuf eth_clk_gbuf ( .CLK(eth_clk_pad_i), .GL(eth_clk_o) ); assign eth_pll_lock = 1'b1; `endif // !`ifdef ETH_CLK_PLL `endif assign sync_eth_rst_n = eth_pll_lock; `else // !`ifdef SYNTHESIS // Buggy looking Actel PLL simulation model (it was drifting when // generating certain frequencies) so we will generate our own during // simulation. reg wb_clk_gen = 0; reg usb_clk_gen = 0; // Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns parameter Tskew_actel_pll_gla = 0.200; assign #Tskew_actel_pll_gla sdram_clk_o = sys_clk_pad_i; always #((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <= async_rst ? 0 : ~wb_clk_gen; always #((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <= async_rst ? 0 : ~usb_clk_gen; assign wb_clk_o = wb_clk_gen; `ifdef USB_CLK assign usb_clk_o = usb_clk_gen; `endif `ifdef ETH_CLK `ifdef ETH_CLK_PLL // Ethernet clock is 125MHz on ORSoC dev board // PLL set to -0.06ns delay model this here wire eth_clk, eth_clk_dly1, eth_clk_dly2; assign #3.5 eth_clk_dly1 = eth_clk_pad_i; assign #3.5 eth_clk_dly2 = eth_clk_dly1; assign #(1 - 0.06)eth_clk = eth_clk_dly2; assign eth_clk_o = eth_clk; `else assign eth_clk_o = eth_clk_pad_i; `endif // !`ifdef ETH_CLK_PLL `endif // `ifdef ETH_CLK reg pll_lock = 0; reg eth_pll_lock = 1; always @(async_rst) if (async_rst) pll_lock = 0; else #300 pll_lock = 1; // Assign synchronous resets assign sync_rst_n = pll_lock; assign sync_eth_rst_n = eth_pll_lock; `endif // !`ifdef SYNTHESIS `endif // `ifdef ACTEL_PLL // // Reset generation // // // Reset generation for wishbone reg [15:0] wb_rst_shr; always @(posedge wb_clk_o or posedge async_rst) if (async_rst) wb_rst_shr <= 16'hffff; else wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)}; assign wb_rst_o = wb_rst_shr[15]; `ifdef VERSATILE_SDRAM // Reset generation for SDRAM controller reg [15:0] sdram_rst_shr; always @(posedge sdram_clk_o or posedge async_rst) if (async_rst) sdram_rst_shr <= 16'hffff; else sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)}; assign sdram_rst_o = sdram_rst_shr[15]; `endif // `ifdef VERSATILE_SDRAM `ifdef ETH_CLK // Reset generation for ethernet SMII reg [15:0] eth_rst_shr; always @(posedge eth_clk_o or posedge async_rst) if (async_rst) eth_rst_shr <= 16'hffff; else eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)}; assign eth_rst_o = eth_rst_shr[15]; `endif // `ifdef ETH_CLK endmodule // clkgen
Go to most recent revision | Compare with Previous | Blame | View Log