Subversion Repositories openrisc_me

 
 
`include "timescale.v"
`include "or1200_defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
 
//
// Top of TB
//
`define TB_TOP orpsoc_testbench
 
//
// Top of DUT
//
`define DUT_TOP `TB_TOP.dut
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP `DUT_TOP.or1200_top0
 
 
`define CPU or1200
`define CPU_cpu or1200_cpu
`define CPU_rf or1200_rf
`define CPU_except or1200_except
`define CPU_ctrl or1200_ctrl
`define CPU_sprs or1200_sprs
`define CPU_ic_top or1200_ic_top
`define CPU_ic_ram or1200_ic_ram
`define CPU_ic_tag or1200_ic_tag
`define CPU_dc_top or1200_dc_top
`define CPU_dc_ram or1200_dc_ram
`define CPU_dc_tag or1200_dc_tag
 
`define CPU_immu_top or1200_immu_top
`define CPU_immu_tlb or1200_immu_tlb
`define CPU_dmmu_top or1200_dmmu_top
`define CPU_dmmu_tlb or1200_dmmu_tlb
 
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
 
`define FT_STIM_MEM_LOC 32'h00000004
`define FT_STIM_GO_WORD 32'h88000000
 
module or1200_ft_stim;
 
   reg debug_on;
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
   task get_ram_word;
      input [31:0] addr;
      output [31:0] insn;
      begin
	 insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
      end
   endtask // get_ram_word
 
   task set_ram_word;
      input [31:0] addr;
      input [31:0] word;
      reg 	   dummy;      
      begin
	 dummy = `RAM_WB_TOP.set_mem32(addr[31:2], word);
      end
   endtask // set_ram_word
 
 
   task wait_for_start;
      reg [31:0] mem_word;
      begin
	 get_ram_word(`FT_STIM_MEM_LOC, mem_word);	 
	 while(mem_word !== `FT_STIM_GO_WORD)
	   begin
 
//	      if (debug_on)
//		$display("%m: Wait for start, read %h",mem_word);
 
	      #100000;
	      get_ram_word(`FT_STIM_MEM_LOC, mem_word);
	   end
      end
   endtask // wait_for_start
 
   task get_command;
      output [31:0] out_cmd;
 
      reg [31:0] mem_word;
      begin
	 get_ram_word(`FT_STIM_MEM_LOC, mem_word);
	 while(mem_word === 32'h0)
	   begin
	      #10000;
 
//	      if (debug_on)
//		$display("%m: get_command %h",mem_word);
 
	      get_ram_word(`FT_STIM_MEM_LOC, mem_word);
	   end
	 out_cmd = mem_word;
      end
   endtask // get_command
 
   task ack_command;
      begin
//	 if (debug_on)
//	   $display("%m: Ack command");
      set_ram_word(`FT_STIM_MEM_LOC, 0);
      end
   endtask // ack_command
 
   task inject_ic_ram_fault;
      input [31:0] cmd;
      reg [23:0]   word_number;
      reg [7:0]    bit_number;
 
      begin
	 // Get line number from command
	 word_number = cmd[15:0];
	 bit_number = cmd[23:16];
	 if (debug_on)
	   $display("%m: inject error into IC RAM word 0x%h, data bit %02d",
		    word_number, bit_number);
 
	 `OR1200_TOP.`CPU_ic_top.`CPU_ic_ram.ic_ram0.gen_parity_err(word_number,
								    -1, 
								    bit_number);
	 ack_command;
      end
   endtask // inject_ic_ram_fault
 
   task inject_ic_tag_fault;
      input [31:0] cmd;
      reg [23:0]   tag_word;
      reg [7:0]    bit_number;      
      begin
	 // Get line number from command
	 tag_word = cmd[15:0];
	 bit_number = cmd[23:16];
	 if (debug_on)
	   $display("%m: inject error into IC tag line 0x%h, data bit %02d",
		    tag_word, bit_number);
 
	 `OR1200_TOP.`CPU_ic_top.`CPU_ic_tag.ic_tag0.gen_parity_err(tag_word,
								    -1, 
								    bit_number);
	 ack_command;
      end
   endtask
 
   task inject_dc_ram_fault;
      input [31:0] cmd;
      reg [23:0]   word_number;
      reg [7:0]    bit_number;
 
      begin
	 // Get line number from command
	 word_number = cmd[15:0];
	 bit_number = cmd[23:16];
	 if (debug_on)
	   $display("%m: inject error into DC RAM word 0x%h, data bit %02d",
		    word_number, bit_number);
 
	 `OR1200_TOP.`CPU_dc_top.`CPU_dc_ram.dc_ram0.gen_parity_err(word_number,
								    bit_number);
	 ack_command;
      end
   endtask
 
   task inject_dc_tag_fault;
      input [31:0] cmd;
      reg [23:0]   tag_word;
      reg [7:0]    bit_number;      
      begin
	 // Get line number from command
	 tag_word = cmd[15:0];
	 bit_number =cmd[23:16];
	 if (debug_on)
	   $display("%m: inject error into DC tag line 0x%h, data bit %02d",
		    tag_word, bit_number);
 
	 `OR1200_TOP.`CPU_dc_top.`CPU_dc_tag.dc_tag0.gen_parity_err(tag_word,
								    -1, 
								    bit_number);
	 ack_command;
      end
   endtask
 
   task inject_immu_fault;
      input tr;
      input [31:0] cmd;
      reg [23:0]   mem_word;
      reg [7:0]    bit_number;      
      begin
	 // Get line number from command
	 mem_word = cmd[15:0];
	 bit_number =cmd[23:16];
	 if (tr)
	   begin
	      if (debug_on)
		$display("%m: inject error into iTLB TR RAM, 0x%h, bit %02d",
			 mem_word, bit_number);
 
   `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.gen_parity_err(
								   mem_word,
								   -1, 
								   bit_number);
	   end
	 else
	   begin
	      if (debug_on)
		$display("%m: inject error into iTLB MR RAM, 0x%h, bit %02d",
			 mem_word, bit_number);
 
   `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.gen_parity_err(
								   mem_word,
								   -1, 
								   bit_number);
 
	   end // else: !if(tr)
 
	 ack_command;
 
      end
   endtask // inject_immu_fault
 
   task inject_dmmu_fault;
      input tr;
      input [31:0] cmd;
      reg [23:0]   mem_word;
      reg [7:0]    bit_number;      
      begin
	 // Get line number from command
	 mem_word = cmd[15:0];
	 bit_number =cmd[23:16];
	 if (tr)
	   begin
	      if (debug_on)
		$display("%m: inject error into dtlb TR RAM, 0x%h, bit %02d",
			 mem_word, bit_number);
 
   `OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_tr_ram.gen_parity_err(
								   mem_word,
								   -1, 
								   bit_number);
	   end
	 else
	   begin
	      if (debug_on)
		$display("%m: inject error into dtlb MR RAM, 0x%h, bit %02d",
			 mem_word, bit_number);
 
   `OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_mr_ram.gen_parity_err(
								   mem_word,
								   -1, 
								   bit_number);
 
	   end // else: !if(tr)
 
	 ack_command;
 
      end
   endtask
 
 
   task inject_rf_fault;
      input [31:0] cmd;
      reg [23:0]   gpr_no;
      reg [7:0]    bit_number;
      begin
	 bit_number =cmd[23:16];
	 gpr_no = cmd[15:0];
 
	 if (debug_on)
	   $display("%m: inject error into register file, r%02d, bit %02d",
		    gpr_no, bit_number);
 
	 `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.gen_parity_err(   gpr_no,
							     -1, 
							     bit_number);
	 `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_b.gen_parity_err(   gpr_no,
							     -1, 
							     bit_number);
 
	 ack_command;
 
      end
   endtask
 
   reg [31:0] cmd;
 
 
`define FT_STIM_CMD_WORD_CMD_POS 31:24
`define FT_STIM_CMD_WORD_CMD_WIDTH 8
`define FT_STIM_CMD_WORD_DATA_POS 23:0
`define FT_STIM_CMD_WORD_DATA_WIDTH 24
 
`define FT_STIM_CMD_IC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h1
`define FT_STIM_CMD_IC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h2
`define FT_STIM_CMD_DC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h3
`define FT_STIM_CMD_DC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h4
 
`define FT_STIM_CMD_DMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h5
`define FT_STIM_CMD_DMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h6
`define FT_STIM_CMD_IMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h7
`define FT_STIM_CMD_IMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h8
 
`define FT_STIM_CMD_RF_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h9
 
`define FT_STIM_CMD_DEBUG_ON `FT_STIM_CMD_WORD_CMD_WIDTH'hff
`define FT_STIM_CMD_DEBUG_OFF `FT_STIM_CMD_WORD_CMD_WIDTH'hfe     
 
 
initial
  begin
     #10;
 
     // Disable to begin with
     debug_on = 1;
 
     // Wait for software to indicate the test is ready to run.
     wait_for_start;
 
     // Ack our receipt of start
     ack_command;
 
     while(1)
       begin
	  cmd = 32'hdeaddead;
 
	  get_command(cmd);
 
	  case(cmd[`FT_STIM_CMD_WORD_CMD_POS])
	    `FT_STIM_CMD_IC_RAM_FAULT: begin
	       inject_ic_ram_fault(cmd);
	    end
	    `FT_STIM_CMD_IC_TAG_FAULT: begin
	       inject_ic_tag_fault(cmd);
	    end
	    `FT_STIM_CMD_DC_RAM_FAULT: begin
	       inject_dc_ram_fault(cmd);
	    end
	    `FT_STIM_CMD_DC_TAG_FAULT: begin
	       inject_dc_tag_fault(cmd);
	    end
	    `FT_STIM_CMD_DMMU_MR_FAULT: begin
	       inject_dmmu_fault(0, cmd);
	    end
	    `FT_STIM_CMD_DMMU_TR_FAULT: begin
	       inject_dmmu_fault(1, cmd);
	    end	    
	    `FT_STIM_CMD_IMMU_MR_FAULT: begin
	       inject_immu_fault(0, cmd);
	    end
	    `FT_STIM_CMD_IMMU_TR_FAULT: begin
	       inject_immu_fault(1, cmd);
	    end
	    `FT_STIM_CMD_RF_FAULT: begin
	       inject_rf_fault(cmd);
	    end
	    `FT_STIM_CMD_DEBUG_ON: begin
	       $display("%m: Debug on");
	       debug_on = 1;
	       ack_command;
	    end
	    `FT_STIM_CMD_DEBUG_OFF: begin
	       $display("%m: Debug off");
	       debug_on = 0;
	       ack_command;
	    end
	    default:
	      begin
		 $display("%m: Unknown command %h", 
			  cmd[`FT_STIM_CMD_WORD_CMD_POS]);
		 #10000;
		 $finish;
	      end
 
	  endcase // case (cmd[`FT_STIM_CMD_WORD_CMD_POS])
 
       end // while (1)
  end // initial begin
 
`endif   
endmodule // or1200_ft_stim