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/*
 Parity error handler
 
 Vector of parity error indicating signals coming in.
 
 We issue reset if certain errors are spotted, and interrupt in the case of
 others.
 
 This module is not intended to be synthesisable, rather to be used in
 conjunction with the or1200_ft_stim testbench module.
 
 */
 
module parity_err_handler(
			  clk,
			  parity_err,
			  wb_rst,
			  reset,
			  interrupt,
			  wb_dat_o,
			  wb_ack_o,
			  wb_stb_i
			  );
   parameter parity_vector_width = 9;
   parameter parity_vector_resets = 1; // Signals at or below this we reset on
 
   input clk;
   input [parity_vector_width-1:0] parity_err;
   input 			   wb_rst;
   output			   reset;
   output reg 			   interrupt;
   output reg [7:0] 		   wb_dat_o;
   output 			   wb_ack_o;
   input 			   wb_stb_i;
 
   reg 				   reset_r;
 
   wire [parity_vector_width-1:0]  parity_err_mask;
 
   assign parity_err_mask = 9'b111100000;
 
   // Signal a reset if signals up to the number indicated by 
   // parity_vector_resets go high.
   always @(clk or wb_rst)
     if (wb_rst)
       reset_r <= 0;
     else
       casez(parity_err[parity_vector_width-1:0])
	 //9'b????1????: reset_r <= 1;
	 //9'b?????1???: reset_r <= 1;
	 //9'b??????1??: reset_r <= 1;
	 //9'b???????1?: reset_r <= 1;
	 9'b????????1: reset_r <= 1;
	 default: reset_r <= 0;
       endcase // casex (parity_err[parity_vector_resets-1:0])
 
   assign reset = reset_r;
 
   always @(posedge reset)
     $display("%m: Reset due to parity error. Vect:%h",parity_err);
 
 
   // Signal an interrupt if signals above number parity_vector_resets go high
   always @(posedge clk)
     begin
	if (wb_rst)
	  interrupt <= 0;
	// Simulate level sensitive interrupt - clear upon read
	else if (parity_err[parity_vector_width-1:parity_vector_resets]
		 & ~parity_err_mask)
	  interrupt <= 1;
	else if (wb_stb_i & wb_ack_o)
	  interrupt <= 0;
     end
 
   assign wb_ack_o = wb_stb_i;
 
   // Data bus output to indicate which thing caused parity error
   always @(posedge clk)
     begin
	if (wb_rst)
	  wb_dat_o <= 0;
	else if (parity_err[parity_vector_width-1:parity_vector_resets])
	  wb_dat_o <= parity_err[parity_vector_width-1:parity_vector_resets];
	else if (wb_ack_o) // Clear data after read
	  wb_dat_o <= 0; 
     end
 
 
 
endmodule // parity_err_handler