URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [generic/] [ft/] [sw/] [board/] [include/] [board.h] - Rev 483
Compare with Previous | Blame | View Log
#ifndef _BOARD_H_ #define _BOARD_H_ #define IN_CLK 50000000 // Hz // // Defines for each core (memory map base, OR1200 interrupt line number, etc.) // #define RAM_BASE 0x00000000 #define RAM_SIZE 0x00100000 // Parity error indicator module. Simple one for this build #define PARERR_BASE 0xe0000000 // Parity error generator IRQ - just for this test design #define PARERR_IRQ 5 // // OR1200 tick timer period define // #define TICKS_PER_SEC 100 #endif