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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [include/] [xilinx_ddr2_params.v] - Rev 627

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   parameter C3_P0_MASK_SIZE           = 16;
   parameter C3_P0_DATA_PORT_SIZE      = 128;
   parameter DEBUG_EN                = 0;       
   parameter C3_MEMCLK_PERIOD        = 3750;       
   parameter C3_CALIB_SOFT_IP        = "TRUE";       
   parameter C3_SIMULATION           = "FALSE";       
   parameter C3_RST_ACT_LOW          = 0;       
   parameter C3_INPUT_CLK_TYPE       = "SINGLE_ENDED";       
   parameter C3_MEM_ADDR_ORDER       = "BANK_ROW_COLUMN";       
   parameter C3_NUM_DQ_PINS          = 16;       
   parameter C3_MEM_ADDR_WIDTH       = 13;       
   parameter C3_MEM_BANKADDR_WIDTH   = 3;
 
   // Simulation parameter defines
   parameter DQ_WIDTH                = 16;
   parameter DQS_WIDTH               = 1;
   parameter DM_WIDTH                = 1;
   parameter CLK_WIDTH               = 1;
   parameter ROW_WIDTH               = 13;
   parameter BANK_WIDTH              = 3;
   parameter CKE_WIDTH               = 1;
   parameter ODT_WIDTH               = 1;
 
 

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