OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [syn/] [xst/] [coregen/] [coregen.cgp] - Rev 727

Go to most recent revision | Compare with Previous | Blame | View Log

SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx45
SET package = csg324
SET speedgrade = -2
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.