URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_idelay_ctrl.v] - Rev 415
Go to most recent revision | Compare with Previous | Blame | View Log
//***************************************************************************** // DISCLAIMER OF LIABILITY // // This file contains proprietary and confidential information of // Xilinx, Inc. ("Xilinx"), that is distributed under a license // from Xilinx, and may be used, copied and/or disclosed only // pursuant to the terms of a valid license agreement with Xilinx. // // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION // ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER // EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT // LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, // MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx // does not warrant that functions included in the Materials will // meet the requirements of Licensee, or that the operation of the // Materials will be uninterrupted or error-free, or that defects // in the Materials will be corrected. Furthermore, Xilinx does // not warrant or make any representations regarding use, or the // results of the use, of the Materials in terms of correctness, // accuracy, reliability or otherwise. // // Xilinx products are not designed or intended to be fail-safe, // or for use in any application requiring fail-safe performance, // such as life-support or safety devices or systems, Class III // medical devices, nuclear facilities, applications related to // the deployment of airbags, or any other applications that could // lead to death, personal injury or severe property or // environmental damage (individually and collectively, "critical // applications"). Customer assumes the sole risk and liability // of any use of Xilinx products in critical applications, // subject only to applicable laws and regulations governing // limitations on product liability. // // Copyright 2006, 2007, 2008 Xilinx, Inc. // All rights reserved. // // This disclaimer and copyright notice must be retained as part // of this file at all times. //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: 3.0 // \ \ Application: MIG // / / Filename: ddr2_idelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: Virtex-5 //Design Name: DDR2 //Purpose: // This module instantiates the IDELAYCTRL primitive of the Virtex-5 device // which continuously calibrates the IDELAY elements in the region in case of // varying operating conditions. It takes a 200MHz clock as an input //Reference: //Revision History: // Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added // on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed // since tools will replicate idelactrl primitives.PK. 11/27/08 //***************************************************************************** `timescale 1ns/1ps module ddr2_idelay_ctrl # ( // Following parameters are for 72-bit RDIMM design (for ML561 Reference // board design). Actual values may be different. Actual parameters values // are passed from design top module ddr2_mig module. Please refer to // the ddr2_mig module for actual values. parameter IODELAY_GRP = "IODELAY_MIG" ) ( input clk200, input rst200, output idelay_ctrl_rdy ); (* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl ( .RDY(idelay_ctrl_rdy), .REFCLK(clk200), .RST(rst200) ); endmodule
Go to most recent revision | Compare with Previous | Blame | View Log