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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_infrastructure.v] - Rev 485
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//***************************************************************************** // DISCLAIMER OF LIABILITY // // This file contains proprietary and confidential information of // Xilinx, Inc. ("Xilinx"), that is distributed under a license // from Xilinx, and may be used, copied and/or disclosed only // pursuant to the terms of a valid license agreement with Xilinx. // // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION // ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER // EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT // LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, // MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx // does not warrant that functions included in the Materials will // meet the requirements of Licensee, or that the operation of the // Materials will be uninterrupted or error-free, or that defects // in the Materials will be corrected. Furthermore, Xilinx does // not warrant or make any representations regarding use, or the // results of the use, of the Materials in terms of correctness, // accuracy, reliability or otherwise. // // Xilinx products are not designed or intended to be fail-safe, // or for use in any application requiring fail-safe performance, // such as life-support or safety devices or systems, Class III // medical devices, nuclear facilities, applications related to // the deployment of airbags, or any other applications that could // lead to death, personal injury or severe property or // environmental damage (individually and collectively, "critical // applications"). Customer assumes the sole risk and liability // of any use of Xilinx products in critical applications, // subject only to applicable laws and regulations governing // limitations on product liability. // // Copyright 2006, 2007, 2008 Xilinx, Inc. // All rights reserved. // // This disclaimer and copyright notice must be retained as part // of this file at all times. //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: 3.0 // \ \ Application: MIG // / / Filename: ddr2_infrastructure.v // /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: Virtex-5 //Design Name: DDR2 //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: // Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and // SINGLE_ENDED added. PK. 6/20/08 // Rev 1.2 - Loacalparam CLK_GENERATOR added and logic for clocks generation // using PLL or DCM added as generic code. PK. 10/14/08 //***************************************************************************** `timescale 1ns/1ps module ddr2_infrastructure # ( // Following parameters are for 72-bit RDIMM design (for ML561 Reference // board design). Actual values may be different. Actual parameters values // are passed from design top module ddr2_mig module. Please refer to // the ddr2_mig module for actual values. parameter CLK_PERIOD = 3000, parameter CLK_TYPE = "DIFFERENTIAL", parameter DLL_FREQ_MODE = "HIGH", parameter RST_ACT_LOW = 1 ) ( input sys_clk_p, input sys_clk_n, input sys_clk, input clk200_p, input clk200_n, input idly_clk_200, output clk0, output clk90, output clk200, output clkdiv0, input sys_rst_n, input idelay_ctrl_rdy, output rst0, output rst90, output rst200, output rstdiv0 ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on PLL/DCM lock status) localparam RST_SYNC_NUM = 25; localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0; localparam CLK_PERIOD_INT = CLK_PERIOD/1000; // By default this Parameter (CLK_GENERATOR) value is "PLL". If this // Parameter is set to "PLL", PLL is used to generate the design clocks. // If this Parameter is set to "DCM", // DCM is used to generate the design clocks. localparam CLK_GENERATOR = "PLL"; wire clk0_bufg; wire clk0_bufg_in; wire clk90_bufg; wire clk90_bufg_in; wire clk200_bufg; wire clk200_ibufg; wire clkdiv0_bufg; wire clkdiv0_bufg_in; wire clkfbout_clkfbin; wire locked; reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */; reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */; reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */; reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */; wire rst_tmp; wire sys_clk_ibufg; wire sys_rst; assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n; assign clk0 = clk0_bufg; assign clk90 = clk90_bufg; assign clk200 = clk200_bufg; assign clkdiv0 = clkdiv0_bufg; generate if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST //*************************************************************************** // Differential input clock input buffers //*************************************************************************** IBUFGDS_LVPECL_25 SYS_CLK_INST ( .I (sys_clk_p), .IB (sys_clk_n), .O (sys_clk_ibufg) ); IBUFGDS_LVPECL_25 IDLY_CLK_INST ( .I (clk200_p), .IB (clk200_n), .O (clk200_ibufg) ); end/* else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST //************************************************************************** // Single ended input clock input buffers //************************************************************************** IBUFG SYS_CLK_INST ( .I (sys_clk), .O (sys_clk_ibufg) ); IBUFG IDLY_CLK_INST ( .I (idly_clk_200), .O (clk200_ibufg) ); // This is being instantiated inside another design. these signals are properly generated elsewhere -- jb end*/ endgenerate assign sys_clk_ibufg = sys_clk; //assign idly_clk_200 = clk200_ibufg; assign clk200_bufg = idly_clk_200; /* BUFG CLK_200_BUFG ( .O (clk200_bufg), .I (clk200_ibufg) ); */ //*************************************************************************** // Global clock generation and distribution //*************************************************************************** generate if (CLK_GENERATOR == "PLL") begin : gen_pll_adv PLL_ADV # ( .BANDWIDTH ("OPTIMIZED"), .CLKIN1_PERIOD (CLK_PERIOD_NS), .CLKIN2_PERIOD (10.000), .CLKOUT0_DIVIDE (CLK_PERIOD_INT), .CLKOUT1_DIVIDE (CLK_PERIOD_INT), .CLKOUT2_DIVIDE (CLK_PERIOD_INT*2), .CLKOUT3_DIVIDE (1), .CLKOUT4_DIVIDE (1), .CLKOUT5_DIVIDE (1), .CLKOUT0_PHASE (0.000), .CLKOUT1_PHASE (90.000), .CLKOUT2_PHASE (0.000), .CLKOUT3_PHASE (0.000), .CLKOUT4_PHASE (0.000), .CLKOUT5_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT5_DUTY_CYCLE (0.500), .COMPENSATION ("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT (CLK_PERIOD_INT), .CLKFBOUT_PHASE (0.0), .REF_JITTER (0.005000) ) u_pll_adv ( .CLKFBIN (clkfbout_clkfbin), .CLKINSEL (1'b1), .CLKIN1 (sys_clk_ibufg), .CLKIN2 (1'b0), .DADDR (5'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .REL (1'b0), .RST (sys_rst), .CLKFBDCM (), .CLKFBOUT (clkfbout_clkfbin), .CLKOUTDCM0 (), .CLKOUTDCM1 (), .CLKOUTDCM2 (), .CLKOUTDCM3 (), .CLKOUTDCM4 (), .CLKOUTDCM5 (), .CLKOUT0 (clk0_bufg_in), .CLKOUT1 (clk90_bufg_in), .CLKOUT2 (clkdiv0_bufg_in), .CLKOUT3 (), .CLKOUT4 (), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (locked) ); end else if (CLK_GENERATOR == "DCM") begin: gen_dcm_base DCM_BASE # ( .CLKIN_PERIOD (CLK_PERIOD_NS), .CLKDV_DIVIDE (2.0), .DLL_FREQUENCY_MODE (DLL_FREQ_MODE), .DUTY_CYCLE_CORRECTION ("TRUE"), .FACTORY_JF (16'hF0F0) ) u_dcm_base ( .CLK0 (clk0_bufg_in), .CLK180 (), .CLK270 (), .CLK2X (), .CLK2X180 (), .CLK90 (clk90_bufg_in), .CLKDV (clkdiv0_bufg_in), .CLKFX (), .CLKFX180 (), .LOCKED (locked), .CLKFB (clk0_bufg), .CLKIN (sys_clk_ibufg), .RST (sys_rst) ); end endgenerate BUFG U_BUFG_CLK0 ( .O (clk0_bufg), .I (clk0_bufg_in) ); BUFG U_BUFG_CLK90 ( .O (clk90_bufg), .I (clk90_bufg_in) ); BUFG U_BUFG_CLKDIV0 ( .O (clkdiv0_bufg), .I (clkdiv0_bufg_in) ); //*************************************************************************** // Reset synchronization // NOTES: // 1. shut down the whole operation if the PLL/ DCM hasn't yet locked (and // by inference, this means that external SYS_RST_IN has been asserted - // PLL/DCM deasserts LOCKED as soon as SYS_RST_IN asserted) // 2. In the case of all resets except rst200, also assert reset if the // IDELAY master controller is not yet ready // 3. asynchronously assert reset. This was we can assert reset even if // there is no clock (needed for things like 3-stating output buffers). // reset deassertion is synchronous. //*************************************************************************** assign rst_tmp = sys_rst | ~locked | ~idelay_ctrl_rdy; // synthesis attribute max_fanout of rst0_sync_r is 10 always @(posedge clk0_bufg or posedge rst_tmp) if (rst_tmp) rst0_sync_r <= {RST_SYNC_NUM{1'b1}}; else // logical left shift by one (pads with 0) rst0_sync_r <= rst0_sync_r << 1; // synthesis attribute max_fanout of rstdiv0_sync_r is 10 always @(posedge clkdiv0_bufg or posedge rst_tmp) if (rst_tmp) rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}}; else // logical left shift by one (pads with 0) rstdiv0_sync_r <= rstdiv0_sync_r << 1; // synthesis attribute max_fanout of rst90_sync_r is 10 always @(posedge clk90_bufg or posedge rst_tmp) if (rst_tmp) rst90_sync_r <= {RST_SYNC_NUM{1'b1}}; else rst90_sync_r <= rst90_sync_r << 1; // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg // synthesis attribute max_fanout of rst200_sync_r is 10 always @(posedge clk200_bufg or negedge locked) if (!locked) rst200_sync_r <= {RST_SYNC_NUM{1'b1}}; else rst200_sync_r <= rst200_sync_r << 1; assign rst0 = rst0_sync_r[RST_SYNC_NUM-1]; assign rst90 = rst90_sync_r[RST_SYNC_NUM-1]; assign rst200 = rst200_sync_r[RST_SYNC_NUM-1]; assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1]; endmodule
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