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//*****************************************************************************
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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application	    : MIG
//  /   /        Filename	    : s3adsp_ddr2_cal_top.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the instantiations cal_ctl and tap_dly.
//*****************************************************************************
 
`timescale 1ns/100ps
 
(* X_CORE_INFO = "mig_v3_61_ddr2_sp3, Coregen 12.4" , 
   CORE_GENERATION_INFO = "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=32, memory_width=8, clk_width=2, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=13'b0010100110011, ext_load_mode_register=13'b0000000000000, language=Verilog, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}" *)
 module s3adsp_ddr2_cal_top
   (
    input        clk0,
    input        clk0dcmlock,
    input        reset,
    output [4:0] tapfordqs,
   // debug signals
    output [4:0] dbg_phase_cnt,
    output [5:0] dbg_cnt,
    output       dbg_trans_onedtct,
    output       dbg_trans_twodtct,
    output       dbg_enb_trans_two_dtct
    );
 
   wire [31:0] 	 flop2_val;
   wire 	 fpga_rst;
 
   assign 	 fpga_rst = (~reset || ~clk0dcmlock);
 
   s3adsp_ddr2_cal_ctl cal_ctl0 
     (
      .clk                    (clk0), 
      .reset                  (fpga_rst), 
      .flop2                  (flop2_val), 
      .tapfordqs              (tapfordqs),
      .dbg_phase_cnt          (dbg_phase_cnt),
      .dbg_cnt                (dbg_cnt),
      .dbg_trans_onedtct      (dbg_trans_onedtct),
      .dbg_trans_twodtct      (dbg_trans_twodtct),
      .dbg_enb_trans_two_dtct (dbg_enb_trans_two_dtct)
      );
 
   s3adsp_ddr2_tap_dly tap_dly0 
     (
      .clk	(clk0), 
      .reset	(fpga_rst), 
      .tapin	(clk0), 
      .flop2	(flop2_val)
      );
 
endmodule