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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application	    : MIG
//  /   /        Filename	    : s3adsp_ddr2_infrastructure_iobs_0.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the FDDRRSE instantiations to the clocks.
//*****************************************************************************
 
`include "s3adsp_ddr2_parameters_0.v"
`timescale 1ns/100ps
 
module s3adsp_ddr2_infrastructure_iobs_0
  (
   input                     clk0,
   output [(`CLK_WIDTH-1):0] ddr2_ck,
   output [(`CLK_WIDTH-1):0] ddr2_ck_n
  );
 
   wire vcc;
   wire gnd;
 
 
 
   wire [`CLK_WIDTH-1 :0]  ddr2_clk_q;
 
   assign  gnd = 1'b0;
   assign  vcc = 1'b1;
 
//---- ***********************************************************
//----     Output DDR generation
//----     This includes instantiation of the output DDR flip flop
//----     for ddr clk's and dimm clk's
//---- ***********************************************************
 
 
 
 
 
 genvar clk_i;
 generate
   for(clk_i = 0; clk_i < `CLK_WIDTH; clk_i = clk_i+1)
   begin: gen_clk
    FDDRRSE clk_inst
     (
      .Q  (ddr2_clk_q[clk_i]),
      .C0 (clk0),
      .C1 (~clk0),
      .CE (vcc),
      .D0 (vcc),
      .D1 (gnd),
      .R  (gnd),
      .S  (gnd)
      );
    end
  endgenerate
 
 
//---- ******************************************
//---- Ouput BUffers for ddr clk's and dimm clk's
//---- ******************************************
 
 
 
 
 
   genvar obuf_i;
   generate
     for(obuf_i = 0; obuf_i < `CLK_WIDTH; obuf_i = obuf_i+1)
     begin: gen_obuf
       OBUFDS OBUFDS_inst
        (
       .I(ddr2_clk_q[obuf_i]),
       .O(ddr2_ck[obuf_i]),
       .OB(ddr2_ck_n[obuf_i])
       );
     end
   endgenerate
 
endmodule