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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application	    : MIG
//  /   /        Filename	    : s3adsp_ddr2_rd_gray_cntr.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	:
//*****************************************************************************
 
`timescale 1ns/100ps
module s3adsp_ddr2_rd_gray_cntr
  (     
   input        clk90,
   input        reset90,
   input        cnt_en,
   output [3:0] rgc_gcnt
    );
 
   wire [3:0] gc_int;
   reg [3:0]  d_in;
   reg  reset90_r;
 
   assign rgc_gcnt = gc_int;
 
 
   always @( posedge clk90 )
     reset90_r <= reset90;
 
   always@(gc_int) begin
      case (gc_int)
        4'b0000:  d_in <= 4'b0001;  //1
        4'b0001:  d_in <= 4'b0011;  //3
        4'b0010:  d_in <= 4'b0110;  //6
        4'b0011:  d_in <= 4'b0010;  //2
        4'b0100:  d_in <= 4'b1100;  //c
        4'b0101:  d_in <= 4'b0100;  //4
        4'b0110:  d_in <= 4'b0111;  //7
        4'b0111:  d_in <= 4'b0101;  //5
        4'b1000:  d_in <= 4'b0000;  //0
        4'b1001:  d_in <= 4'b1000;  //8
        4'b1010:  d_in <= 4'b1011;  //b
        4'b1011:  d_in <= 4'b1001;  //9
        4'b1100:  d_in <= 4'b1101;  //d
        4'b1101:  d_in <= 4'b1111;  //f
        4'b1110:  d_in <= 4'b1010;  //a
        4'b1111:  d_in <= 4'b1110;  //e
        default : d_in <= 4'b0001;  //1
      endcase
   end
 
   FDRE bit0
     (
      .Q  (gc_int[0]),
      .C  (clk90),
      .CE (cnt_en),
      .D  (d_in[0]),
      .R  (reset90_r)
      );
 
   FDRE bit1
     (
      .Q  (gc_int[1]),
      .C  (clk90),
      .CE (cnt_en),
      .D  (d_in[1]),
      .R  (reset90_r)
      );
 
   FDRE bit2
     (
      .Q  (gc_int[2]),
      .C  (clk90),
      .CE (cnt_en),
      .D  (d_in[2]),
      .R  (reset90_r)
      );
 
   FDRE bit3
     (
      .Q  (gc_int[3]),
      .C  (clk90),
      .CE (cnt_en),
      .D  (d_in[3]),
      .R  (reset90_r)
      );
 
endmodule