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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [tap_defines.v] - Rev 848
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////////////////////////////////////////////////////////////////////// //// //// //// tap_defines.v //// //// //// //// //// //// This file is part of the JTAG Test Access Port (TAP) //// //// http://www.opencores.org/projects/jtag/ //// //// //// //// Author(s): //// //// Igor Mohor (igorm@opencores.org) //// //// //// //// //// //// All additional information is avaliable in the README.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 - 2003 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: tap_defines.v,v $ // Revision 1.2 2004/01/27 10:00:33 mohor // Unused registers removed. // // Revision 1.1 2003/12/23 14:52:14 mohor // Directory structure changed. New version of TAP. // // // // Define IDCODE Value `define IDCODE_VALUE 32'h14951185 // Length of the Instruction register `define IR_LENGTH 4 // Supported Instructions `define EXTEST 4'b0000 `define SAMPLE_PRELOAD 4'b0001 `define IDCODE 4'b0010 `define DEBUG 4'b1000 `define MBIST 4'b1001 `define BYPASS 4'b1111
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