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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Rev 594
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's DC RAMs //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://opencores.org/project,or1k //// //// //// //// Description //// //// Instatiation of DC RAM blocks. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // // $Log: or1200_dc_ram.v,v $ // Revision 2.0 2010/06/30 11:00:00 ORSoC // Minor update: // Coding style changed. // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_dc_ram( // Reset and clock clk, rst, `ifdef OR1200_BIST // RAM BIST mbist_si_i, mbist_so_o, mbist_ctrl_i, `endif // Internal i/f addr, en, we, datain, dataout ); parameter dw = `OR1200_OPERAND_WIDTH; parameter aw = `OR1200_DCINDX; // // I/O // input clk; input rst; input [aw-1:0] addr; input en; input [3:0] we; input [dw-1:0] datain; output [dw-1:0] dataout; `ifdef OR1200_BIST // // RAM BIST // input mbist_si_i; input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control output mbist_so_o; `endif `ifdef OR1200_NO_DC // // Data cache not implemented // assign dataout = {dw{1'b0}}; `ifdef OR1200_BIST assign mbist_so_o = mbist_si_i; `endif `else // // Instantiation of RAM block // or1200_spram_32_bw # ( .aw(`OR1200_DCINDX), .dw(dw) ) dc_ram ( `ifdef OR1200_BIST // RAM BIST .mbist_si_i(mbist_si_i), .mbist_so_o(mbist_so_o), .mbist_ctrl_i(mbist_ctrl_i), `endif .clk(clk), .ce(en), .we(we), .addr(addr), .di(datain), .doq(dataout) ); `endif endmodule // or1200_dc_ram
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