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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_tlb.v] - Rev 483
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's Instruction TLB //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instantiation of ITLB. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: or1200_immu_tlb.v,v $ // Revision 2.0 2010/06/30 11:00:00 ORSoC // Minor update: // Bugs fixed, coding style changed. // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" // // Insn TLB // module or1200_immu_tlb( // Rst and clk clk, rst, // I/F for translation tlb_en, vaddr, hit, ppn, uxe, sxe, ci, `ifdef OR1200_BIST // RAM BIST mbist_si_i, mbist_so_o, mbist_ctrl_i, `endif `ifdef OR1200_RAM_PARITY // Parity error indicator p_err, `endif // SPR access spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o ); parameter dw = `OR1200_OPERAND_WIDTH; parameter aw = `OR1200_OPERAND_WIDTH; // // I/O // // // Clock and reset // input clk; input rst; // // I/F for translation // input tlb_en; input [aw-1:0] vaddr; output hit; output [31:`OR1200_IMMU_PS] ppn; output uxe; output sxe; output ci; `ifdef OR1200_BIST // // RAM BIST // input mbist_si_i; input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; output mbist_so_o; `endif `ifdef OR1200_RAM_PARITY output [1:0] p_err; `endif // // SPR access // input spr_cs; input spr_write; input [31:0] spr_addr; input [31:0] spr_dat_i; output [31:0] spr_dat_o; // // Internal wires and regs // wire [`OR1200_ITLB_TAG] vpn; wire v; wire [`OR1200_ITLB_INDXW-1:0] tlb_index; wire tlb_mr_en; wire tlb_mr_we; wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in; wire tlb_tr_en; wire tlb_tr_we; wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in; `ifdef OR1200_RAM_PARITY wire [`OR1200_ITLBMRW-1+2:0] tlb_mr_ram_out; wire [`OR1200_ITLBTRW-1+2:0] tlb_tr_ram_out; `else wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out; wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out; `endif // BIST `ifdef OR1200_BIST wire itlb_mr_ram_si; wire itlb_mr_ram_so; wire itlb_tr_ram_si; wire itlb_tr_ram_so; `endif `ifdef OR1200_RAM_PARITY wire [1:0] p_err_wire; reg p_err_en; `endif // // Implemented bits inside match and translate registers // // itlbwYmrX: vpn 31-19 v 0 // itlbwYtrX: ppn 31-13 uxe 7 sxe 6 // // itlb memory width: // 19 bits for ppn // 13 bits for vpn // 1 bit for valid // 2 bits for protection // 1 bit for cache inhibit // // Enable for Match registers // assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]); // // Write enable for Match registers // assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]; // // Enable for Translate registers // assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]); // // Write enable for Translate registers // assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]; // // Output to SPRS unit // assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ? {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} : (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ? {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} : 32'h00000000; // // Assign outputs from Match registers // assign {vpn, v} = tlb_mr_ram_out[`OR1200_ITLBMRW-1:0]; // // Assign to Match registers inputs // assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]}; // // Assign outputs from Translate registers // assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out[`OR1200_ITLBTRW-1:0]; // // Assign to Translate registers inputs // assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS], spr_dat_i[`OR1200_ITLBTR_UXE_BITS], spr_dat_i[`OR1200_ITLBTR_SXE_BITS], spr_dat_i[`OR1200_ITLBTR_CI_BITS]}; // // Generate hit // assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v `ifdef OR1200_RAM_PARITY & !p_err `endif ; // // TLB index is normally vaddr[18:13]. If it is SPR access then index is // spr_addr[5:0]. // assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX]; `ifdef OR1200_BIST assign itlb_mr_ram_si = mbist_si_i; assign itlb_tr_ram_si = itlb_mr_ram_so; assign mbist_so_o = itlb_tr_ram_so; `endif `ifdef OR1200_RAM_PARITY always @(posedge clk) if (rst) p_err_en <= 0; else p_err_en <= (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we); assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0; `endif // // Instantiation of ITLB Match Registers // or1200_spram # ( .aw(6), `ifdef OR1200_RAM_PARITY .dw(16) `else .dw(14) `endif ) itlb_mr_ram ( .clk(clk), .rst(rst), `ifdef OR1200_BIST // RAM BIST .mbist_si_i(itlb_mr_ram_si), .mbist_so_o(itlb_mr_ram_so), .mbist_ctrl_i(mbist_ctrl_i), `endif .ce(tlb_mr_en), .we(tlb_mr_we), //.oe(1'b1), .addr(tlb_index), `ifdef OR1200_RAM_PARITY .p_err(p_err_wire[0]), .di({2'b00,tlb_mr_ram_in}), `else .di(tlb_mr_ram_in), `endif .doq(tlb_mr_ram_out) ); // // Instantiation of ITLB Translate Registers // or1200_spram # ( .aw(6), `ifdef OR1200_RAM_PARITY .dw(24) `else .dw(22) `endif ) itlb_tr_ram ( .clk(clk), .rst(rst), `ifdef OR1200_BIST // RAM BIST .mbist_si_i(itlb_tr_ram_si), .mbist_so_o(itlb_tr_ram_so), .mbist_ctrl_i(mbist_ctrl_i), `endif .ce(tlb_tr_en), .we(tlb_tr_we), //.oe(1'b1), .addr(tlb_index), `ifdef OR1200_RAM_PARITY .p_err(p_err_wire[1]), .di({2'b00,tlb_tr_ram_in}), `else .di(tlb_tr_ram_in), `endif .doq(tlb_tr_ram_out) ); endmodule