URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_parity_chk.v] - Rev 483
Compare with Previous | Blame | View Log
////////////////////////////////////////////////////////////////////// //// //// //// OR1200 Parity Checking //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://opencores.org/project,or1k //// //// //// //// Description //// //// Parity bit checking, combinatorial. Presumes single bit of //// //// parity supplied to check against. Signals error on parity //// //// mismatch. //// //// //// //// To Do: //// //// //// //// Author(s): //// //// - Julius Baxter, julius@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2011 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_parity_chk ( d_i, p_i, err_o ); // Width of data we check parity for. parameter dw = 8; input [dw-1:0] d_i; // Data word in input p_i; // Parity bit in output err_o; // Error indicator out // Is nice if X's don't propegate through here during simulation, so use // !== assign err_o = ((^d_i[dw-1:0]) !== p_i); endmodule // or1200_parity_chk